DSALPHA-3

Jul 09

©

2009 RF Solutions Ltd.

Page 13

ALPHA-TX

ALPHA-RX

r2..r0: select DRSSI threshold

r2

r1

r0

RSSIsetth [dBm]

0

0

0

-103

0

0

1

-97

0

1

0

-91

0

1

1

-85

1

0

0

-79

1

0

1

-73

1

1

0

-67

1

0

1

-61

The actual DRSSI threshold is related to LNA setup:

en: Enable the receiver

5

．

．

．

． Wake-Up Timer Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

1

r4

r3

r2

r1

r0

m7

m6

m5

m4

m3

m2

m1

m0

E196h

The wake-up period is determined by:

For continual operation, bit ‘et’ must be cleared and set

6

．

．

．

． Low Duty-Cycle Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

0

0

1

1

0

0

d6

d5

d4

d3

d2

d1

d0

en

CCOEh

d6..d0: Set duty cycle D.C.= (D * 2 +1) / M *100%

en：Enable low duty cycle mode

7

．

．

．

． Low Battery Detector and Microcontroller Clock Divider Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

0

0

0

0

1

0

d2

d1

d0

t4

t3

t2

t1

t0

C200h

d2..d0: select frequency of CLK pin

d2

d1

d0

Clock frequency[MHz]

0

0

0

1

0

0

1

1.25

0

1

0

1.66

0

1

1

2

1

0

0

2.5

1

0

1

3.33

1

1

0

5

1

1

1

10

CLK signal is derive form crystal oscillator and it can be applied to MCU clock in to save a second

crystal. If not used, please set bit “dc” to disable CLK output

To integrate the load capacitor internal can not only save cost, but also adjust reference frequency

by software

t4..t0: Set threshold voltage of Low battery detector： Vlb=2.2+T*0.1 [V]