DSALPHA-3

Jul 09

©

2009 RF Solutions Ltd.

Page 15

ALPHA-TX

ALPHA-RX

10

．

．

．

．

Data Rate Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

0

0

1

0

0

0

cs

r6

r5

r4

r3

r2

r1

r0

C823h

r7..r0: Set data rate

BR=10000000/29/：R+1：/：1+cs*7：

11

．

．

．

．

Output and FIFO mode Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

0

0

1

1

1

0

f3

f2

f1

f0

s1

s0

ff

fe

CE85h

f3..f0: Set FIFO interrupt level

s1..s0: select FIFO fill start condition

s1

s0

0

0

VDI

0

1

Sync-word

1

0

VDI & Sync-word

1

1

Always

ff: Enable FIFO fill

fe: Enable FIFO function

12.Reset Mode Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

0

1

1

0

1

0

0

0

0

0

0

0

0

dr

DAOOh

Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a

system reset. For a more detailed description see the Reset modes section.

13.Status Read Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

0

x

x

x

x

x

x

x

x

x

x

x

x

x

x

x

-

This command starts with a 0 and be used to read internal status register