AD7887ARM datasheet(5/24 Pages) AD

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AD7887

Rev. D | Page 5 of 24

TIMING SPECIFICATIONS1

Table 2.

Limit at TMIN, TMAX

(A, B Versions)

Parameter

4.75 V to 5.25 V

2.7 V to 3.6 V

Unit

Description

fSCLK2

MHz max

tCONVERT

14.5 × tSCLK

tACQ

1.5 × tSCLK

Throughput time = tCONVERT + tACQ = 16 tSCLK

ns min

CS to SCLK setup time

t23

ns max

Delay from CS until DOUT three-state disabled

t33

100

ns max

Data access time after SCLK falling edge

ns min

Data setup time prior to SCLK rising edge

ns min

Data valid to SCLK hold time

0.4 × tSCLK

ns min

SCLK high pulse width

0.4 × tSCLK

ns min

SCLK low pulse width

t84

ns max

CS rising edge to DOUT high impedance

μs typ

Power-up time from shutdown

1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2 Mark/space ratio for the SCLK input is 40/60 to 60/40.

3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.

4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

200µA

IOL

200µA

IOH

1.6V

OUTPUT

50pF

Figure 2. Load Circuit for Digital Output Timing Specifications

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