AD7887

Rev. D | Page 11 of 24

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7887 is a fast, low power, 12-bit, single-supply, single-

channel/dual-channel ADC. The part can be operated from a

3 V (2.7 V to 3.6 V) supply or from a 5 V (4.75 V to 5.25 V) supply.

When operated from either a 5 V or 3 V supply, the AD7887 is

capable of throughput rates of 125 kSPS when provided with a

2 MHz clock.

The AD7887 provides the user with an on-chip, track/hold

analog-to-digital converter reference and a serial interface

housed in an 8-lead package. The serial clock input accesses data

from the part and provides the clock source for the successive

approximation ADC. The part can be configured for single-

channel or dual-channel operation. When configured as a

the AD7887 is configured for two input channels, the input

If single-channel operation is required, the AD7887 can be

operated in a read-only mode by tying the DIN line permanently

to GND. For applications where the user wants to change the

mode of operation or wants to operate the AD7887 as a dual-

channel ADC, the DIN line can be used to clock data into the

part’s control register.

CONVERTER OPERATION

The AD7887 is a successive approximation ADC built around a

charge-redistribution DAC. Figure 8 and Figure 9 show simplified

schematics of the ADC. Figure 8 shows the ADC during its

acquisition phase. SW2 is closed and SW1 is in Position A, the

comparator is held in a balanced condition, and the sampling

capacitor acquires the signal on AIN.

(REF IN/REF OUT)/2

SAMPLING

CAPACITOR

COMPARATOR

ACQUISITION

PHASE

SW1

A

SW2

AGND

B

AIN

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

Figure 8. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 9), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the charge-redistribution DAC

are used to add and subtract fixed amounts of charge from the

sampling capacitor to bring the comparator back into a balanced

condition. When the comparator is rebalanced, the conversion

is complete. The control logic generates the ADC output code.

Figure 10 shows the ADC transfer function.

(REF IN/REF OUT)/2

SAMPLING

CAPACITOR

COMPARATOR

CONVERSION

PHASE

SW1

A

SW2

AGND

B

CHARGE

REDISTRIBUTION

DAC

CONTROL

LOGIC

Figure 9. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7887 is straight binary. The

designed code transitions occur at successive integer LSB values

ideal transfer characteristic for the AD7887 is shown in Figure

10.

0V

ANALOG INPUT

111 ... 000

011 ... 111

0.5LSB

111 ... 111

111 ... 110

000 ... 010

000 ... 001

000 ... 000

Figure 10. Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 11 shows a typical connection diagram for the AD7887.

The GND pin is connected to the analog ground plane of the

16-bit word with four leading zeros followed by the MSB of the

12-bit result. For applications where power consumption is of

concern, the automatic power-down at the end of conversion

should be used to improve power performance. See the Modes

of Operation section.

DOUT

DIN

SCLK

CS

AIN1

AIN2

GND

0.1µF

10µF

SUPPLY 2.7V

TO 5.25V

SERIAL

INTERFACE

AD7887

INPUT

µC/µP

Figure 11. Typical Connection Diagram