IDT1337

REA LTIME CLOCK WITH SERIAL INTERFACE

RTC

7

IDT1337

REV J 111009

Table 2. Alarm Mask Bits

Special-Purpose Registers

The IDT1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.

Control Register (0Eh)

Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to

a logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.

Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the

square wave has been enabled. Table 3 shows the square-wave frequencies that can be selected with the RS bits.

These bits are both set to logic 1 (32 kHz) when power is first applied.

Table 3. SQW/INT Output

DY/DT

Alarm 1 Register Mask Bits (Bit 7)

Alarm Rate

A1M4

A1M3

A1M2

A1M1

X

1111

Alarm once per second.

X

1110

Alarm when seconds match.

X

1100

Alarm when minutes and seconds match.

X

1000

Alarm when hours, minutes, and seconds match.

0

0000

Alarm when date, hours, minutes, and seconds match.

1

0000

Alarm when day, hours, minutes, and seconds match.

DY/DT

Alarm 2 Register Mask Bits (Bit 7)

Alarm Rate

A2M4

A2M3

A2M2

X

1

1

1

Alarm once per minute (00 seconds of every minute).

X

1

1

0

Alarm when minutes match.

X

1

0

0

Alarm when hours and minutes match.

0

0

0

0

Alarm when date, hours, and minutes match.

1

0

0

0

Alarm when day, hours, and minutes match.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EOSC

0

0

RS2

RS1

INTCN

A2IE

A1IE

INTCN

RS2

RS1

SQW/INTB Output

A2IE

00

0

1 Hz

X

0

0

1

4.096 kHz

X

0

1

0

8.192 kHz

X

0

1

1

32.768 kHz

X

1X

X

A2F

1