IDT1337

RTC

14

IDT1337

REV J 111009

Note 1: Limits at -40°C are guaranteed by design and are not production tested.

Note 2: SCL only.

Note 3: SDA, INTA, and SQW/INTB.

Note 6: SQW enabled.

Note 7: Specified with the SQW function disabled by setting INTCN = 1.

Note 8: Using recommended crystal on X1 and X2.

Note 9: The device is fully accessible when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <

1.8 V.

Note 10: After this period, the first clock pulse is generated.

the SCL signal) to bridge the undefined region of the falling edge of SCL.

signal.

then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such

Note 15: Guaranteed by design. Not production tested.

Rise Time of Both SDA and SCL

Signals, Note 14

Fast Mode

300

ns

Standard Mode

1000

Fall Time of Both SDA and SCL Signals,

Note 14

Fast Mode

300

ns

Standard Mode

300

Setup Time for STOP Condition

Fast Mode

0.6

µs

Standard Mode

4.0

Capacitive Load for Each Bus Line,

Note 14

400

pF

I/O Capacitance (SDA, SCL)

Note 15

10

pF

32.768 kHz Clock Accuracy with

External Crystal

±10

ppm

32.768 kHz Clock Accuracy with

Internal Crystal

(crystal accuracy

±20ppm)

±30

ppm

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units