ICS663

PLL BUILDING BLOCK

PLL BUILDING BLOCK

IDT™ / ICS™ PLL BUILDING BLOCK

2

ICS663

REV E 012006

Pin Assignment

VCO Post Divide Select Table

0 = connect pin directly to ground

1 = connect pin directly to VDD

Pin Descriptions

1

2

3

FBIN

4

VDD

GND

CLK

LF

SEL

LFR

8

7

6

5

REFIN

8 Pin (150 mil) SOIC

SEL

VCO Post

Divide

08

12

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

FBIN

Input

Feedback clock input. Connect the output of the feedback divider to

this pin. Falling edge triggered.

2

VDD

Power

VDD. Connect to +3.3 V or +5 V.

3

GND

Power

Connect to ground.

4

LF

Input

Loop filter connection (refer to Figure 1 on Page 5).

When using the phase detector block only, this pin serves as the

charge pump output.

When using the VCO block only, this pin serves as VCO input control

voltage.

5

LFR

Input

Loop filter return (refer to Figure 1 on Page 5).

6

SEL

Input

Select pin for VCO post divide, as per above table.

7

CLK

Output

Clock output.

8

REFIN

Input

Reference clock input. Connect the input clock to this pin. Falling edge

triggered.