ICS663

PLL BUILDING BLOCK

PLL BUILDING BLOCK

IDT™ / ICS™ PLL BUILDING BLOCK

6

ICS663

REV E 012006

Determining the Loop Filter Values

Calculating these values is best illustrated by an example.

Using the example in Figure 1, we can synthesize 20 MHz

from a 200 kHz input.

The phase locked loop may be approximately described by

the following equations:

Bandwidth

Damping factor,

where:

N = Total feedback divide from VCO,

including the internal VCO post divider

As a general rule, the bandwidth should be at least 20 times

less than the reference frequency, i.e.,

In this example, using the above equation, bandwidth

should be less than or equal to 10 kHz. By setting the

determined since all other variables are known. In the

example of Figure 1, N = 200, comprising the divide by 2 on

the chip (VCO post divider) and the external divide by 100.

Therefore, the bandwidth equation becomes:

Choosing a damping factor of 0.7 (a minimal damping factor

than can be used to ensure fast lock time), damping factor

equation becomes:

charge pump and should be approximately 1/20th the size

To summarize, the loop filter components are:

⋅⋅

(

)

2

π N

⋅

------------------------------------------

=

ζ

2

------

⋅⋅

N

------------------------------------

=

BW REFIN

() 20

⁄

≤

0,000

⋅⋅

2

π 200

⋅

--------------------------------------

=

.7

25 000

,

2

-------------------

200

2.5

C

⋅⋅

200

------------------------------------

=

⁄

≅