数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

PCF8563TS/5 数据表(PDF) 22 Page - NXP Semiconductors

部件名 PCF8563TS/5
功能描述  Real-time clock/calendar
PDF  50 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8563TS/5 数据表(HTML) 22 Page - NXP Semiconductors

Back Button PCF8563TS/5 Datasheet HTML 18Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 19Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 20Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 21Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 22Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 23Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 24Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 25Page - NXP Semiconductors PCF8563TS/5 Datasheet HTML 26Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 50 page
background image
PCF8563
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
22 of 50
NXP Semiconductors
PCF8563
Real-time clock/calendar
8.11 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator is
stopped. In the reset state the I2C-bus logic is initialized including the address pointer and
all registers are set according to Table 27. I2C-bus communication is not possible during
reset.
[1]
Registers marked x are undefined at power-up and unchanged by subsequent resets.
8.11.1 Power-On Reset (POR) override
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this
mode requires that the I2C-bus pins, SDA and SCL, are toggled in a specific order as
shown in Figure 13. All timings are required minimums.
Once the override mode has been entered, the device immediately stops, being reset,
and normal operation may commence i.e. entry into the EXT_CLK test mode via I2C-bus
access. The override mode may be cleared by writing logic 0 to TESTC. TESTC must be
set to logic 1 before re-entry into the override mode is possible. Setting TESTC to logic 0
during normal operation has no effect except to prevent entry into the POR override
mode.
Table 27.
Register reset value[1]
Address
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_status_1
00001000
01h
Control_status_2
00000000
02h
VL_seconds
1
xxxxxxx
03h
Minutes
xxxxxxxx
04h
Hours
xxxxxxxx
05h
Days
xxxxxxxx
06h
Weekdays
xxxxxxxx
07h
Century_months
xxxxxxxx
08h
Years
xxxxxxxx
09h
Minute_alarm
1
xxxxxxx
0Ah
Hour_alarm
1
xxxxxxx
0Bh
Day_alarm
1
xxxxxxx
0Ch
Weekday_alarm
1
xxxxxxx
0Dh
CLKOUT_control
1
xxxxx0
0
0Eh
Timer_control
0
xxxxx1
1
0Fh
Timer
xxxxxxxx



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com