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PCF8563TS/5 数据表(PDF) 34 Page - NXP Semiconductors

部件名 PCF8563TS/5
功能描述  Real-time clock/calendar
PDF  50 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

PCF8563TS/5 数据表(HTML) 34 Page - NXP Semiconductors

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PCF8563
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 10 — 3 April 2012
34 of 50
NXP Semiconductors
PCF8563
Real-time clock/calendar
13. Dynamic characteristics
[1]
CL is a calculation of Ctrim and COSCO in series:
.
[2]
Unspecified for fCLKOUT = 32.768 kHz.
[3]
All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage
swing of VSS to VDD.
[4]
A detailed description of the I2C-bus specification is given in Ref. 11 “UM10204”.
[5]
I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
Table 30.
Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =40 k; CL = 8 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator
COSCO
capacitance on pin OSCO
15
25
35
pF
f
osc/fosc
relative oscillator frequency variation
V
DD =200 mV;
Tamb =25 C
-0.2
-ppm
Quartz crystal parameters (f = 32.768 kHz)
Rs
series resistance
-
-
100
k
CL
load capacitance
parallel
[1] 7
-
12.5
pF
Ctrim
trimmer capacitance
external;
on pin OSCI
5-
25
pF
CLKOUT output
CLKOUT
duty cycle on pin CLKOUT
[2] -50
-%
I2C-bus timing characteristics (see Figure 28)[3][4]
fSCL
SCL clock frequency
[5] -
-
400
kHz
tHD;STA
hold time (repeated) START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated START condition
0.6
-
-
s
tLOW
LOW period of the SCL clock
1.3
-
-
s
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
tr
rise time of both SDA and SCL signals
standard-mode
-
-
1
s
fast-mode
-
-
0.3
s
tf
fall time of both SDA and SCL signals
-
-
0.3
s
tBUF
bus free time between a STOP and START
condition
1.3
-
-
s
Cb
capacitive load for each bus line
-
-
400
pF
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tSU;STO
set-up time for STOP condition
0.6
-
-
s
tw(spike)
spike pulse width
on bus
-
-
50
ns
C
L
C
trim
C
OSCO

C
trim
C
OSCO
+

-----------------------------------------
=



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