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TLV2211CDBVR 数据表(PDF) 26 Page - Texas Instruments |
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TLV2211CDBVR 数据表(HTML) 26 Page - Texas Instruments |
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26 / 31 page ![]() TLV2211, TLV2211Y Advanced LinCMOS RAILTORAIL MICROPOWER SINGLE OPERATIONAL AMPLIFIERS SLOS156E − MAY 1996 − REVISED SEPTEMBER 2006 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION driving large capacitive loads (continued) The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 54). To use equation 1, UGBW must be approximated from Figure 54. 10 k Ω 10 k Ω VDD −/ GND VDD + Rnull CL VI + − Figure 54. Series-Resistance Circuit driving heavy dc loads The TLV2211 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-rail output devices. This device is specified to sink 500 µA and source 250 µA at VDD = 3 V and VDD = 5 V at a maximum quiescent IDD of 25 µA. This provides a greater than 90% power efficiency. When driving heavy dc loads, such as 10 k Ω, the positive edge can experience some distortion under slewing conditions. This condition can be seen in Figure 39. This condition is affected by three factors: D Where the load is referenced. When the load is referenced to either rail, this condition does not occur. The distortion occurs only when the output signal swings through the point where the load is referenced. Figure 40 illustrates two 10-k Ω load conditions. The first load condition shows the distortion seen for a 10-k Ω load tied to 2.5 V. The third load condition shows no distortion for a 10-kΩ load tied to 0 V. D Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 40 illustrates the difference seen on the output for a 10-k Ω load and a 100-kΩ load with both tied to 2.5 V. D Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input edge rates. |
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