PCM1723

6

SBAS057A

www.ti.com

TYPICAL CONNECTION DIAGRAM

Figure 1 illustrates the typical connection diagram for the

PCM1723 in an MPEG-2 application. The 27MHz master

programmable system clock is generated by the PCM1723

PLL, with SCKO used to drive the MPEG-2 decoder system

clock input. The standard audio signals (data, bit clock, and

word clock) are generated in the decoder from the PCM1723

system clock, providing synchronization of audio and video

signals.

PLL CIRCUIT

The PCM1723 has a programmable internal PLL circuit, as

shown in Figure 2. The PLL is designed to accept a 27MHz

master clock or crystal oscillator and generate all internal

system clocks required to operate the digital filter and

∆Σ

is used, XTO must be connected to GND. In both cases, the

signal amplitude on XTI must satisfy the specification de-

scribed in Figure 3. Therefore, careful C1 and C2 determi-

nation is required to keep this specification satisfied when

FIGURE 1. Connection Diagram for External Master Clock in a Typical MPEG-2 Application.

Oscillator

XTO

XTI

MCKO

PLL Generated

System Clock Out

Frequency

Selection ROM

Phase Detector

and Loop Filter

VCO

Sampling Frequency Selection

256f

N Counter

M Counter

24

1

5

2

FIGURE 2. PLL Block Diagram.

FIGURE 3. XTI Input Timing.

t

CH

XTI

1/27MHz

t

CL

1.2V

t

t

I

I

0.4V

DIN

BCKIN

LRCIN

SCKO

SERO

SCKO

LRCKO

SYSCKI

XTI

17

16

18

2

6

7

8

9

ML

MC

MD

RSTB

14

XTO

23

22

21

3

11

15

10

1

24

27MHz CLK OUT

+

10

µF

Post

LPF

Post

LPF

Analog

Mute

Analog

Mute

STRB

SCKO

SDO

PIO

System

Controller

Rch Analog Out

Lch Analog Out

12

13

Audio

Decoder

Buffer

256/384f

S

AGND

PGND DGND

V

CC

+5V Analog

+5V Analog

V

DD

V

CP

V

V

ZERO

CAP

PCM1723

Master

PLL

or

PCR

NOTE: (1) SCR: System Clock Reference

PCR: Program Clock Reference