PCM1723

10

SBAS057A

www.ti.com

OPE controls the operation of the DAC: when OPE is LOW,

the DAC will convert all non-zero input data. If the input

data is continuously zero for 65,536 cycles of BCKIN, the

output will be forced to zero only if IZD is HIGH. When

OPE is HIGH, the output of the DAC will be forced to

bipolar zero, irrespective of any input data.

IZD = 1

IZD = 0

DATA INPUT

DAC OUTPUT

Zero

Other

Normal

Zero

Other

Normal

TABLE VI. Infinite Zero Detection (IZD) Function.

RSTB = HIGH

RSTB = LOW

SOFTWARE

MODE

DATA INPUT

DAC OUTPUT

INPUT

Zero

Controlled by OPE and IZD

Enabled

Other

Controlled by OPE and IZD

Enabled

Zero

Disabled

Other

Disabled

TABLE VII. Reset (RSTB) Function.

Bits 3 (IW0) and 4 (IW1) are used to determine input word

resolution. PCM1723 can be set up for input word resolu-

tions of 16, 20, or 24 bits:

Bit 4 (IW1)

Bit 3 (IW0)

Input Resolution

0

0

16-bit Data Word

0

1

20-bit Data Word

1

0

24-bit Data Word

1

1

Reserved

Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.

The output of PCM1723 can be programmed for 16 different

states, as shown in Table VIII.

PL0

PL1

PL2

PL3

Lch OUTPUT

Rch OUTPUT

NOTE

0

0

0

0

MUTE

MUTE

MUTE

0

0

0

1

MUTE

R

0

0

1

0

MUTE

L

0

0

1

1

MUTE

(L + R)/2

0

1

0

0

R

MUTE

0

101

R

R

0

1

1

0

R

L

REVERSE

0

1

1

1

R

(L + R)/2

1

0

0

0

L

MUTE

1

0

0

1

L

R

STEREO

1

010

L

L

1

0

1

1

L

(L + R)/2

1

1

0

0

(L + R)/2

MUTE

1

1

0

1

(L + R)/2

R

1

1

1

0

(L + R)/2

L

1

1

1

1

(L + R)/2

(L + R)/2

MONO

TABLE VIII. Programmable Output Format.

REGISTER 3 (A1 = 1, A0 = 1)

B15 B14 B13 B12 B11 B10 B9

B8 B7

B6

B5

B4

B3

B2

B1 B0

res

res res res res

A1

A0

Register 3 is used to control input data format and polarity,

attenuation channel control, system clock frequency, sam-

pling frequency, and infinite zero detection.

format. A LOW on bit 0 sets the format to Normal (MSB-

first, right-justified Japanese format), and a HIGH sets the

used to select the polarity of LRCIN (sample rate clock).

When bit 1 is LOW, left channel data are assumed when

LRCIN is in a HIGH phase and right channel data are

assumed when LRCIN is in a LOW phase. When bit 1 is

HIGH, the polarity assumption is reversed.

Bit 2 (ATC) is used for controlling the attenuator. When

bit 2 is HIGH, the attenuation data loaded in program

Register 0 are used for both left and right channels. When

bit 2 is LOW, the attenuation data for each register are

applied separately to left and right channels.

Bit 3 (SYS) is the system clock selection. When bit 3 is

Bits 4 (DSR0) and 5 (DSR1) are used to control multiples

of the sampling rate:

DSR1

DSR0

Multiple

0

0

Normal

32/44.1/48kHz

0

1

Double

64/88.2/96kHz

1

0

One-half

16/22.05/24kHz

1

1

Reserved

Not Defined

Bits 6 (SF0) and 7 (SF1) are used to select the sampling

frequency. Frequency selection must be made with an

interval time greater than 20

µs.

SF1

SF0

Sampling Frequency

0

0

44.1kHz group

22.05/44.1/88.2kHz

0

1

48kHz group

24/48/96kHz

1

0

32kHz group

16/32/64kHz

1

1

Reserved

Not Defined

Bit 8 is used to control the infinite zero detection function

(IZD).

When IZD is LOW, the zero detect circuit is off. Under

this condition, no automatic muting will occur if the input

is continuously zero. When IZD is HIGH, the zero detect

feature is enabled. If the input data are continuously zero

for 65,536 cycles of BCKIN, the output will be immedi-

detection feature is used to avoid noise which may occur

when the input is DC. When the output is forced to bipolar

zero, there may be an audible click. PCM1723 allows the

zero detect feature to be disabled so the user can imple-

ment an external muting circuit.

NOTE: (1)

∆∑ is disconnected from output amplifier.

NOTES: (1)

∆∑ is disconnected from output amplifier.

(2)

∆∑ is connected to output amplifier.