ADAV4622BSTZ datasheet(21/28 Pages) AD

21 / 28 page

ADAV4622

Rev. B | Page 21 of 2

FUNCTIONAL DESCRIPTIONS

SIF PROCESSOR

Supported SIF Standards

The ADAV4622 supports all worldwide standards, as shown in

Table 6.

Table 6. ADAV4622 Worldwide SIF Standards

System

Sound

SC1 (MHz)

SC2 (MHz)

BTSC

4.5

–

BTSC

4.5

–

EIAJ

4.5

–

4.5

4.724

5.5

5.742

NICAM

5.5

5.85

Mono

6.0

–

NICAM

6.0

6.552

DK1

6.5

6.258

DK2

6.5

6.742

DK3

6.5

5.742

NICAM

6.5

5.85

Mono

6.5

–

NICAM

6.5

5.85

SIF Demodulation

Figure 22 shows a block diagram of the SIF demodulation

block. The selected SIF input signal is digitized by an ADC with

a sample rate of 24.576 MHz. An AGC is included to ensure

that for even low level signals, the full range of the ADC is used.

The digitized input is passed to the SIF demodulator for

demodulating. The outputs of the demodulator are then passed

to the internal audio processor. Internally, the audio processor

runs at a 48 kHz sampling frequency. When NICAM is selected,

an internal SRC upsamples the 32 kHz NICAM signal to the

audio processor rate of 48 kHz.

SIF Processor Configuration

The ADAV4622 supports automatic standard detection, which

is enabled by default. The ASD controller configures the SIF

processor with the optimum register settings based on the

detected standard. If the user prefers to operate in manual mode,

or if the user prefers to use an external ASD loop, all of the ASD

status registers are available.

MASTER CLOCK OSCILLATOR

Internally, the ADAV4622 operates synchronously to the master

MCLKI input. All internal system clocks are generated from

this single clock input using an internal PLL. This MCLKI input

can also be generated by an external crystal oscillator connected

to the MCLKI/XIN pin or by using a simple crystal resonator

connected across MCLKI/XIN and XOUT. By default, the

master clock frequency is 24.576 MHz; however, by using the

internal dividers, an MCLKI of 12.288 MHz, 6.144 MHz, and

3.072 MHz are also supported.

OSC

DIVIDER

DIVIDER WORD

[÷8, ÷4, ÷2, ÷1]

3.072MHz

PLL

REFERENCE

CLOCK

MASTER CLOCK FREQUENCY

[24.576MHz, 12.288MHz,

6.144MHz, 3.072MHz]

I2C

EXTERNAL CLOCK/

CRYSTAL

Figure 21. Master Clock

SIF_IN2

SIF_IN1

SIF INPUT

4.5MHz ~ 6.742MHz

AGC

ADC

24.576MHz

FM/DQPSK/AM

DEMOD

SC1

SC2

SIF

PARAMETERS

ASD

Figure 22. SIF Demodulation

ADAV4622BSTZ 数据表(PDF) 21 Page - Analog Devices

ADAV4622BSTZ 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载

链接网址

ADAV4622BSTZ 数据表(PDF) 21 Page - Analog Devices

ADAV4622BSTZ 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表 下载

链接网址

数据表下载