LIS3DSH datasheet(19/53 Pages) STMICROELECTRONICS

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LIS3DSH

Application hints

Doc ID 022405 Rev 1

19/53

Application hints

Figure 5.

LIS3DSH electrical connection

The device core is supplied through the Vdd line while the I/O pins are supplied through the

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF) should be placed

as near as possible to pin 14 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper

behavior of the IC (refer to

Figure 5). It is possible to remove Vdd maintaining Vdd_IO

without blocking the communication bus, in this condition the measurement chain is

powered off.

The functionality of the device and the measured acceleration data is selectable and

accessible through the I2C or SPI interfaces. When using the I2C, CS must be tied high.

4.1

Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com.

10µF

Vdd

100nF

GND

Vdd_IO

INT1/DRDY

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

TOP VIEW

INT 2

AM10211V1

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