LIS3DSH datasheet(34/53 Pages) STMICROELECTRONICS

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LIS3DSH

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Doc ID 022405 Rev 1

The BDU bit is used to inhibit the output registers update until both upper and lower register

parts are read. In default mode (BDU=‘0’) the output register values are updated

continuously. If for any reason it is not sure whether to read faster than the output data rate it

is recommended to set the BDU bit to ‘1’. In this way the content of output registers is not

updated until both MSb and LSb are read avoiding the reading of values related to a

different sample time.

8.6

CTRL_REG5 (24h)

Control register 5.

8.7

CTRL_REG6 (25h)

Control register 6.

Table 25.

Control register 5

BW2

BW1

FSCALE2

FSCALE1

FSCALE0

ST2

ST1

SIM

Table 26.

Control register 5 description

BW2:BW1

Anti-aliasing filter bandwidth. Default value: 00

00=800 Hz; 01=400 Hz; 10:=200 Hz; 11:=50 Hz)

FSCALE2:0

Full-scale selection. Default value: 00

000=+/- 2G; 001=+/- 4G; 010=+/- 6G; 011=+/- 8G; 100=+/- 16G

ST2:1

Self-test enable. Default value: 00

00=self-test disabled;

SIM

SPI serial interface mode selection. Default value: 0

0=4-wire interface; 1:=3-wire interface

Table 27.

Self-test mode selection

ST2

ST1

Self test mode

Normal mode

Positive sign self-test

Negative sign self-test

Not allowed

Table 28.

Control register 6

BOOOT

FIFO_EN

WTM_EN

ADD_

INC

P1_

EMPTY

P1_WTM

P1_OVER

RUN

P2_

BOOT

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