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AD8400ARZ100 数据表(PDF) 13 Page - Analog Devices |
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AD8400ARZ100 数据表(HTML) 13 Page - Analog Devices |
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13 / 32 page ![]() AD8400/AD8402/AD8403 Rev. E | Page 13 of 32 Table 9. AD8403 Pin Function Descriptions Pin No. Mnemonic Description 1 AGND2 Analog Ground 2.1 2 B2 Terminal B RDAC 2. 3 A2 Terminal A RDAC 2. 4 W2 Wiper RDAC 2, Addr = 012. 5 AGND4 Analog Ground 4.1 6 B4 Terminal B RDAC 4. 7 A4 Terminal A RDAC 4. 8 W4 Wiper RDAC 4, Addr = 112. 9 DGND Digital Ground.1 10 SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor 1 through Variable Resistor 4. 11 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target DAC register. 12 SDI Serial Data Input. 13 SDO Serial Data Output. Open drain transistor requires a pull-up resistor. 14 CLK Serial Clock Input, Positive Edge Triggered. 15 RS Active Low Reset to Midscale. Sets RDAC registers to 80H. 16 VDD Positive Power Supply. Specified for operation at both 3 V and 5 V. 17 AGND3 Analog Ground 3.1 18 W3 Wiper RDAC 3, Addr = 102. 19 A3 Terminal A RDAC 3. 20 B3 Terminal B RDAC 3. 21 AGND1 Analog Ground 1.1 22 W1 Wiper RDAC 1, Addr = 002. 23 A1 Terminal A RDAC 1. 24 B1 Terminal B RDAC 1. 1 All AGND pins must be connected to DGND. |
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