PLL Frequency Synthesizer

Data Sheet

ADF4106

Rev. E

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FEATURES

6.0 GHz bandwidth

2.7 V to 3.3 V power supply

tuning voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65

Programmable charge pump currents

Programmable antibacklash pulse width

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

APPLICATIONS

Broadband wireless access

Satellite systems

Instrumentation

Wireless LANS

Base stations for wireless radios

GENERAL DESCRIPTION

The ADF4106 frequency synthesizer can be used to implement

local oscillators in the up-conversion and down-conversion

sections of wireless receivers and transmitters. It consists of a

low noise, digital phase frequency detector (PFD), a precision

charge pump, a programmable reference divider, programmable

A counter and B counter, and a dual-modulus prescaler (P/P + 1).

The A (6-bit) counter and B (13-bit) counter, in conjunction

with the dual-modulus prescaler (P/P + 1), implement an N

divider (N = BP + A). In addition, the 14-bit reference counter

input. A complete phase-locked loop (PLL) can be implemented

if the synthesizer is used with an external loop filter and voltage

controlled oscillator (VCO). Its very high bandwidth means

that frequency doublers can be eliminated in many high

frequency systems, simplifying system architecture and

reducing cost.

FUNCTIONAL BLOCK DIAGRAM

CLK

DATA

LE

24-BIT INPUT

REGISTER

CE

AGND

DGND

14-BIT

R COUNTER

R COUNTER

LATCH

22

14

FUNCTION

LATCH

A, B COUNTER

LATCH

FROM

FUNCTION

LATCH

PRESCALER

P/P + 1

N = BP + A

LOAD

LOAD

13-BIT

B COUNTER

6-BIT

A COUNTER

6

19

13

M3 M2 M1

MUX

HIGH Z

MUXOUT

CPGND

CP

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

REFERENCE

CHARGE

PUMP

CURRENT

SETTING 1

ADF4106

CPI3 CPI2 CPI1

CPI6 CPI5 CPI4

CURRENT

SETTING 2

Figure 1.