ADXL362BCCZ-R2 datasheet(34/44 Pages) AD

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ADXL362

Data Sheet

Rev. B | Page 34 of 44

POWER CONTROL REGISTER

Address: 0x2D, Reset: 0x00, Name: POWER_CTL

Table 18. Bit Descriptions for POWER_CTL

Bits

Bit Name

Settings

Description

Reset

Access

Reserved

Reserved.

0x0

EXT_CLK

External Clock. See the Using an External Clock section for additional details.

0x0

1 = the accelerometer runs off the external clock provided on the INT1 pin.

[5:4]

LOW_NOISE

Selects Power vs. Noise Tradeoff:

0x0

Normal operation (reset default).

Low noise mode.

Ultralow noise mode.

Reserved.

WAKEUP

Wake-Up Mode. See the Operating Modes section for a detailed

description of wake-up mode.

0x0

1 = the part operates in wake-up mode.

AUTOSLEEP

Autosleep. Activity and inactivity detection must be in linked mode or

loop mode (LINK/LOOP bits in ACT_INACT_CTL register) to enable

autosleep; otherwise, the bit is ignored. See the Motion Detection section

for details.

0x0

1 = autosleep is enabled, and the device enters wake-up mode

automatically upon detection of inactivity.

[1:0]

MEASURE

Selects Measurement Mode or Standby.

0x0

Standby.

Reserved.

Measurement mode.

Reserved.

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