SL3ICS1002FUG datasheet(5/51 Pages) NXP

5 / 51 page

139037

All information provided in this document is subject to legal disclaimers.

Product data sheet

COMPANY PUBLIC

Rev. 3.7 — 9 October 2012

139037

5 of 51

NXP Semiconductors

SL3ICS1002/1202

UCODE G2XM and G2XL

Wafer layout and pinning information

6.1 Wafer layout

(1) X-scribe line width: 56.4

m

(2) Y-scribe line width: 56.4

m

(3) Chip step, x-length: 488.0

m

(4) Chip step, y-length: 470,0

m

(5) Bump to bump distance X (TP1 - RFN): 351,0

m

(6) Bump to bump distance Y (RFN - RFP): 333,0

m

(7) Distance bump to metal sealring X: 40,3

m

(8) Distance bump to metal sealring Y: 40,3

m

Bump size X x Y: 60

m x 60 m

Fig 2.

Wafer layout and pinning information

001aai346

not to scale!

(1)

(7)

(2)

(8)

(5)

(6)

(4)

(3)

TP2

TP1

RFN

RFP

SL3ICS1002FUG 数据表(PDF) 5 Page - NXP Semiconductors

SL3ICS1002FUG 数据表(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

数据表下载