MRF49XA-ISLASHT datasheet(71/102 Pages) MICROCHIP

71 / 102 page

Preliminary

DS70590C-page 71

MRF49XA

3.18.1

INTERRUPT MODE

The user can define the FIFO interrupt level (the

number of received bits) which generates the FINT

when the level is exceeded. In this case, the Status bits

report the changed FIFO status.

3.18.2

POLLING MODE

When the FSEL signal is low, the FIFO output is

connected directly to the SDO pin and its contents are

clocked out by the SCK pin. Set the FIFO interrupt level

to 1. In this case, as long as FINT indicates received

bits in the FIFO, the microcontroller continues to take

the bits away. When FINT goes low, no more bits need

to be taken.

An SPI read command (Receiver FIFO Read

Command) is also available to read out the contents of

the FIFO. See Figure 3-19 for a simple receiver FIFO

read, in Polling mode, on SPI lines.

FIGURE 3-19:

FIFO READ EXAMPLE WITH FINT POLLING

The registers associated with reception are:

•STSREG (see Register 2-1)

• GENCREG (see Register 2-2)

• RXCREG (see Register 2-7)

• FIFORSTREG (see Register 2-10)

• PMCREG (see Register 2-13)

TABLE 3-4:

RECEIVE PIN FUNCTION VS. OPERATION MODE

Mode

Bit Setting

Function

Pin 6

Pin 7

Receive

FIFOEN = 0

Receiver FIFO Disabled

RX Data Output

RX Data Clock Output

FIFOEN = 1

Receiver FIFO Enabled

FSEL Input

(RX data FIFO can be

accessed)

FINT Output

FO + 2

FO + 3

FO + 1

FIFO OUT

FO + 4

FIFO Read Out

012

SCK

SDO

FINT

FSEL

Note: During FIFO access, fSCK cannot be

higher than fref/4, where fref is the crystal

oscillator frequency. If the duty cycle of

the clock signal is not 50%, the shorter

period of the clock pulse should be at

least 2/fref.

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