DSPIC33FJMC202ESS datasheet(151/330 Pages) MICROCHIP

151 / 330 page

DS70283K-page 151

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

13.0 INPUT CAPTURE

The input capture module is useful in applications

requiring frequency (period) and pulse measurement.

The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

devices support up to eight input capture channels.

The input capture module captures the 16-bit value of

the selected Time Base register when an event occurs

at the ICx pin. The events that cause a capture event

are listed below in three categories:

Simple Capture Event modes:

- Capture timer value on every falling edge of

input at ICx pin

- Capture timer value on every rising edge of

input at ICx pin

Capture timer value on every edge (rising and

falling).

Prescaler Capture Event modes:

- Capture timer value on every 4th rising edge

of input at ICx pin

- Capture timer value on every 16th rising

edge of input at ICx pin

Each input capture channel can select one of two

16-bit timers (Timer2 or Timer3) for the time base.

The selected timer can use either an internal or

external clock.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

• 4-word FIFO buffer for capture values

- Interrupt optionally generated after 1, 2, 3 or

4 buffer locations are filled

• Use of input capture to provide additional sources

of external interrupts

FIGURE 13-1:

INPUT CAPTURE BLOCK DIAGRAM

Note 1: This data sheet summarizes the features

of the dsPIC33FJ32MC202/204 and

dsPIC33FJ16MC304 family of devices. It

is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to

Section 12. “Input Capture” (DS70198)

of the “dsPIC33F/PIC24H Family Refer-

ence Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

ICxBUF

ICx Pin

ICM<2:0> (ICxCON<2:0>)

Mode Select

Set Flag ICxIF

(in IFSn Register)

TMR2 TMR3

Edge Detection Logic

FIFO

R/W

Logic

ICxI<1:0>

ICOV, ICBNE (ICxCON<4:3>)

ICxCON

Interrupt

Logic

System Bus

From 16-bit Timers

ICTMR

(ICxCON<7>)

Prescaler

Counter

(1, 4, 16)

and

Clock Synchronizer

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

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