DSPIC33FJMC202ESS datasheet(156/330 Pages) MICROCHIP

156 / 330 page

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DS70283K-page 156

14.1

Output Compare Modes

Configure the Output Compare modes by setting the

appropriate Output Compare Mode bits (OCM<2:0>) in

the Output Compare Control register (OCxCON<2:0>).

Table 14-1 lists the different bit settings for the Output

Compare modes. Figure 14-2 illustrates the output

compare operation for various modes. The user

application must disable the associated timer when

writing to the output compare control registers to avoid

malfunctions.

TABLE 14-1:

OUTPUT COMPARE MODES

FIGURE 14-2:

OUTPUT COMPARE OPERATION

Note:

See Section 13. “Output Compare”

(DS70209) in the “dsPIC33F/PIC24H

Family Reference Manual” (DS70209) for

OCxR and OCxRS register restrictions.

OCM<2:0>

Mode

OCx Pin Initial State

OCx Interrupt Generation

000

Module Disabled

Controlled by GPIO register

—

001

Active-Low One-Shot

OCx Rising edge

010

Active-High One-Shot

OCx Falling edge

011

Toggle Mode

Current output is maintained

OCx Rising and Falling edge

100

Delayed One-Shot

OCx Falling edge

101

Continuous Pulse mode

OCx Falling edge

110

PWM mode without fault

protection

0, if OCxR is zero

1, if OCxR is non-zero

No interrupt

111

PWM mode with fault protection 0, if OCxR is zero

1, if OCxR is non-zero

OCFA Falling edge for OC1 to OC4

OCxRS

TMRy

OCxR

Timer is reset on

period match

Continuous Pulse Mode

(OCM = 101)

PWM Mode

(OCM = 110 or 111)

Active-Low One-Shot

(OCM = 001)

Active-High One-Shot

(OCM = 010)

Toggle Mode

(OCM = 011)

Delayed One-Shot

(OCM = 100)

Output Compare

Mode enabled

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