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DSPIC33FJMC202ESS 数据表(PDF) 166 Page - Microchip Technology |
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DSPIC33FJMC202ESS 数据表(HTML) 166 Page - Microchip Technology |
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166 / 330 page  dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DS70283K-page 166 © 2007-2012 Microchip Technology Inc. REGISTER 15-5: PWMxCON1: PWM CONTROL REGISTER 1(2) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PMOD3 PMOD2 PMOD1 bit 15 bit 8 U-0 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — PEN3H(1) PEN2H(1) PEN1H(1) — PEN3L(1) PEN2L(1) PEN1L(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 PMOD3:PMOD1: PWM I/O Pair Mode bits 1 = PWM I/O pin pair is in the Independent PWM Output mode 0 = PWM I/O pin pair is in the Complementary Output mode bit 7 Unimplemented: Read as ‘0’ bit 6-4 PEN3H:PEN1H: PWMxH I/O Enable bits(1) 1 = PWMxH pin is enabled for PWM output 0 = PWMxH pin disabled, I/O pin becomes general purpose I/O bit 3 Unimplemented: Read as ‘0’ bit 2-0 PEN3L:PEN1L: PWMxL I/O Enable bits(1) 1 = PWMxL pin is enabled for PWM output 0 = PWMxL pin disabled, I/O pin becomes general purpose I/O Note 1: Reset condition of the PENxH and PENxL bits depends on the value of the PWMPIN Configuration bit in the FPOR Configuration register. 2: PWM2 supports only 1 PWM I/O pin pair. |
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