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MCR03EZPFX1002 数据表(PDF) 21 Page - International Rectifier

部件名 MCR03EZPFX1002
功能描述  HIGHLY EFFICIENT INTEGRATED SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS
PDF  32 Pages
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制造商  IRF [International Rectifier]
网页  http://www.irf.com
标志 IRF - International Rectifier

MCR03EZPFX1002 数据表(HTML) 21 Page - International Rectifier

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Rev 16.0
21
PD-97660
IR3831WMPbF
Tantalum
Ceramic
F
LC<Fo<FESR
Type III
Electrolytic
Tantalum
FLC<FESR<Fo<Fs/2
Type II
Output
Capacitor
F
ESR vs Fo
Compensator
Type
Tantalum
Ceramic
F
LC<Fo<FESR
Type III
Electrolytic
Tantalum
FLC<FESR<Fo<Fs/2
Type II
Output
Capacitor
F
ESR vs Fo
Compensator
Type
The compensation network has three poles and
two zeros and they are expressed as follows:
Cross over frequency is expressed as:
Fig.14. Type III Compensation network and
its asymptotic gain plot
(30)
..........
*
*
)
(
*
*
.....(29)
..........
..........
..........
..........
*
*
(28)
.....
..........
*
*
*
*
)
.......(27
..........
..........
..........
..........
*
*
......(26)
..........
..........
..........
..........
..........
..........
8
7
10
8
7
2
4
3
1
3
3
3
4
3
4
3
3
7
10
2
1
2
1
2
1
2
1
2
1
2
1
2
1
0
R
C
R
R
C
F
C
R
F
C
R
C
C
C
C
R
F
C
R
F
F
Z
Z
P
P
P
π
π
π
π
π
π
≅
+
=
=
≅
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
+
=
=
=
(31)
..
..........
..........
..........
*
*
*
*
*
o
o
osc
in
o
C
L
V
V
C
R
F
π
2
1
7
3
=
The
higher
the
crossover
frequency,
the
potentially faster the load transient response.
However, the crossover frequency should be low
enough to allow attenuation of switching noise.
Typically, the control loop bandwidth or crossover
frequency is selected such that
The DC gain should be large enough to provide
high DC-regulation accuracy. The phase margin
should be greater than 45o for overall stability.
For this design we have:
V
in=12V
V
o=0.75V
V
osc=1.8V
Vp=0.75V
L
o=0.6 uH
C
o=8x22uF, ESR=3mOhm each
It must be noted here that the value of the
capacitance used in the compensator design
must be the small signal value. For instance, the
small signal capacitance of the 22uF capacitor
used in this design is 12uF at 0.75 VDC bias and
400 kHz frequency. It is this value that must be
used for all computations related to the
compensation. The small signal value may be
obtained from the manufacturer’s datasheets,
design tools or SPICE models. Alternatively, they
may also be inferred from measuring the power
stage transfer function of the converter and
measuring the double pole frequency F
LC and
using equation (16) to compute the small signal
C
o.
These result to:
F
LC=20.97 kHz
F
ESR=4.4 MHz
F
s/2=200 kHz
Select crossover frequency: F
o= 60 kHz
Since F
LC<Fo<Fs/2<FESR, TypeIII is selected to
place the pole and zeros.
(
)
s
o
F
F
*
1/10
~
1/5
≤
VOUT
VREF
R9
R8
R10
C7
C3
C4
R3
Ve
FZ1
FZ2
FP2
FP3
E/A
Zf
ZIN
Frequency
Gain(dB)
H(s) dB
Fb
Comp
Based on the frequency of the zero generated by
the output capacitor and its ESR, relative to
crossover frequency, the compensation type can
be different. The table below shows the
compensation
types
and
location
of
the
crossover frequency.



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