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Functional Description

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

For example, if your system requires three configuration pages and includes two

FPGAs, each page will store two SRAM Object Files (.sof) for a total of six .sof in the

configuration device.

Furthermore, all EPC device configuration schemes (PS, FPP, and concurrent PS) are

supported with the page-mode feature. The number of pages, devices, or both, that

can be configured using a single EPC device is only limited by the size of the flash

memory.

f For more information about the page-mode feature implementation and

programming file generation steps using the Quartus II software, refer to the Altera

Enhanced Configuration Devices.

Real-Time Decompression

EPC devices support on-chip real time decompression of configuration data. FPGA

configuration data is compressed by the Quartus II software and stored in the EPC

device. During configuration, the decompression engine inside the EPC device will

decompress or expand configuration data. This feature increases the

effective-configuration density of the EPC device up to 7, 15, or 30 Mb in the EPC4,

EPC8, and EPC16 devices, respectively.

The EPC device also supports a parallel 8-bit data bus to the FPGA to reduce

configuration time. However, in some cases, the FPGA data-transfer time is limited by

the flash-read bandwidth. For example, when configuring an APEX II device in FPP

(byte-wide data per cycle) mode at a configuration speed of 66 MHz, the FPGA write

bandwidth is equal to 8 bits × 66 MHz = 528 Mbps. The flash read interface, however,

is limited to approximately 10 MHz (since the flash access time is ~90 ns). This

translates to a flash-read bandwidth of 16 bits × 10 MHz = 160 Mbps. Hence, the

configuration time is limited by the flash-read time.

When configuration data is compressed, the amount of data that needs to be read out

of the flash is reduced by about 50%. If 16 bits of compressed data yields 30 bits of

uncompressed data, the flash-read bandwidth increases to

30 bits × 10 MHz = 300 Mbps, reducing overall configuration time.

You can enable the controller's decompression feature in the Quartus II software,

Configuration Device Options

window by turning on Compression Mode.

1 The decompression feature supported in the EPC devices is different from the

decompression feature supported by the Stratix II FPGAs and the Cyclone series.

When configuring Stratix II FPGAs or the Cyclone series using EPC devices, Altera

recommends enabling decompression in Stratix II FPGAS or the Cyclone series only

for faster configuration.

The compression algorithm used in Altera devices is optimized for FPGA

configuration bitstreams. Since FPGAs have several layers of routing structures (for

high performance and easy routability), large amounts of resources go unused. These

unused routing and logic resources as well as un-initialized memory structures result

in a large number of configuration RAM bits in the disabled state. Altera's proprietary

compression algorithm takes advantage of such bitstream qualities.

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