Page 24

Pin Description

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

WP#

Input

because it could cause contention.

and to allow programming of the flash-bottom boot block, which is required when

programming the device using the Quartus II software.

used.

Supply

Block erase, full-chip erase, word write, or lock-bit configuration power supply.

flash interface.

RY/BY#

Open-Drain Output

Flash asserts this pin when a write or erase operation is complete. This pin is not

connected to the controller. RY/BY# is only available in Sharp flash-based EPC8

and EPC16. (2)

Leave this pin floating when the external flash interface is not used.

BYTE#

Input

Flash byte-enable pin and is only available for EPC devices in the 100-pin PQFP

package.

external flash interface (the controller uses the flash in 16-bit mode). For Intel

pull-up resistor.

Notes to Table 9:

(1) These pins can be driven to 12 V during production testing of the flash memory. Since the controller cannot tolerate the 12-V level, connections

from the controller to these pins are not made internal to the package. Instead they are available as two separate pins. You must connect the

two pins at the board level (for example, on the PCB, connect the C-WE# pin from controller to F-WE# pin from the flash memory).

(2) For more information, refer to the PCN0506: Addition of Intel Flash Memory As Source For EPC4, EPC8 and EPC16 Enhanced Configuration

Table 10. JTAG Interface Pins and Other Required Controller Pins (Part 1 of 2)

Pin Name

Pin Type

Description

TDI

Input

JTAG data input pin.

TDO

Output

JTAG data output pin.

Do not connect this pin if the JTAG circuitry is not used (leave this pin floating).

TCK

Input

JTAG clock pin.

Connect this pin to GND if the JTAG circuitry is not used.

TMS

Input

JTAG mode select pin.

PGM[2..0]

Input

These three input pins select one of the eight pages of configuration data to

configure the FPGAs in the system.

Connect these pins on the board to select the page specified in the Quartus II

software when generating the EPC device POF. PGM[2] is the MSB. The default

selection is page 0; PGM[2..0]=000. These pins must not be left floating.

Table 9. External Flash Interface Pins (Part 2 of 2)

Pin Name

Pin Type

Description