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USB 2.0 HSIC High-Speed Hub Controller Optimized for Portable Applications

Datasheet

SMSC USB3503A

Revision 1.1 (02-07-13)

DATASHEET

Chapter 1 General Description

The SMSC USB3503 is a low-power, USB 2.0 hub controller with HSIC upstream connectivity and

three USB 2.0 downtream ports. The USB3503 operates as a hi-speed hub and supports low-speed,

full-speed, and hi-speed downstream devices on all of the enabled downstream ports.

The USB3503 has been specifically optimized for mobile embedded applications. The pin-count has

been reduced by optimizing the USB3503 for mobile battery-powered embedded systems where power

consumption, small package size, and minimal BOM are critical design requirements. Standby mode

power has been minimized. Instead of a dedicated crystal, reference clock inputs are aligned to mobile

applications. Flexible integrated power regulators ease integration into battery powered devices. All

required resistors on the USB ports are integrated into the hub. This includes all series termination

resistors on D+ and D– pins and all required pull-down resistors on D+ and D– pins.

The USB3503 includes programmable features such as:

MultiTRAKTM Technology, which utilizes a dedicated Transaction Translator (TT) per port to maintain

consistent full-speed data throughput regardless of the number of active downstream connections.

MultiTRAKTM outperforms conventional USB 2.0 hubs with a single TT in USB full-speed data transfers.

PortMap, which provides flexible port mapping and disable sequences. The downstream ports of a

USB3503 hub can be reordered or disabled in any sequence to support multiple platform designs with

minimum effort. For any port that is disabled, the USB3503 hub controllers automatically reorder the

remaining ports to match the USB host controller’s port numbering scheme.

PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows

direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the

USB differential signals on the PCB.

PHYBoost, which provides programmable levels of Hi-Speed USB

signal drive strength in the downstream port transceivers. PHYBoost

attempts to restore USB signal integrity in a compromised system

environment. The graphic on the right shows an example of Hi-

Speed USB eye diagrams before and after PHYBoost signal integrity

restoration.

VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal

receive sensitivity. This capability allows operation in a sub-optimal system environment, such as when

a captive USB cable is used.

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