Arizona Microtek, Inc.

AZP53

Low Phase Noise Sine Wave/CMOS

to LVPECL Buffer/Translator

www.azmicrotek.com

+1-480-962-5881

3

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Mar 2013, Rev 2.2

The AZP53 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as

active high enable or active low enable to oscillator designers. Table 2 details the differences between the parts to assist

designers in selecting the optimal part for their design.

Table 3 lists the specific AZP53 functional operation.

Figure 2 plots the S-parameters of the D input. S-parameter and IBIS model files for the AZP53 are also available for

download.

Table 2 - AZP51-54 & AZP63 Family

Part Number

Divide Ratio

EN Logic

EN pull-

up/pull-down

Bandwidth

AZP51

÷1

active HIGH

Pull-up

> 800MHz

AZP52

÷2

active HIGH

Pull-up

> 800MHz

AZP53

Selectable ÷1 or ÷2

selectable

selectable

> 800MHz

AZP54

÷1

active LOW

Pull-down

> 800MHz

AZP63

Selectable ÷1 or ÷2

selectable

selectable

≥ 1GHz

Table 3 - AZP53 Functional Operation, ÷1 mode

Inputs

Outputs

Part Number

EN_SEL

EN

D

Q

Q

AZP53

Low

Low

High

High High

Low

High

Low

Low

Low

High

High High

Low

Low

DIV_SEL

Divide Ratio

÷1

High

÷2