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AZP53 数据表(PDF) 4 Page - Arizona Microtek, Inc

部件名 AZP53
功能描述  Low Phase Noise Sine Wave / CMOS to LVPECL Buffer / Translator
PDF  13 Pages
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制造商  AZM [Arizona Microtek, Inc]
网页  http://azmicrotek.com
标志 AZM - Arizona Microtek, Inc

AZP53 数据表(HTML) 4 Page - Arizona Microtek, Inc

  AZP53_13 Datasheet HTML 1Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 2Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 3Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 4Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 5Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 6Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 7Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 8Page - Arizona Microtek, Inc AZP53_13 Datasheet HTML 9Page - Arizona Microtek, Inc Next Button
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Arizona Microtek, Inc.
AZP53
Low Phase Noise Sine Wave/CMOS
to LVPECL Buffer/Translator
www.azmicrotek.com
+1-480-962-5881
4
Request a Sample
Mar 2013, Rev 2.2
Figure 2- S11, Parameters, D Input
INPUT TERMINATION
The D input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least
750mVpp ensures the AZP53 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle
on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation.
D
VDD/2
10k
Ω
Input signal
A/R
Figure 3 - Input Termination



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