Rev. 1.0 / Nov. 2012

13

IDD and IDDQ Specification Parameters and Test Conditions

IDD and IDDQ Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure

1. shows the setup and test load for IDD and IDDQ measurements.

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IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,

IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls

of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.

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IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all

VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-

rents.

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Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can

be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In

DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one

merged-power layer in Module PCB.

For IDD and IDDQ measurements, the following definitions apply:

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“MID_LEVEL” is defined as inputs are VREF = VDD/2.

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Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.

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Basic IDD and IDDQ Measurement Conditions are described in Table 2.

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Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.

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IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-

ited to setting

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RON = RZQ/7 (34 Ohm in MR1);

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RTT_Nom = RZQ/6 (40 Ohm in MR1);

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RTT_Wr = RZQ/2 (120 Ohm in MR2);

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TDQS Feature disabled in MR1

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Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time

before actual IDD or IDDQ measurement is started.

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Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}

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Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}