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MCP41010E/P 数据表(PDF) 21 Page - Microchip Technology |
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MCP41010E/P 数据表(HTML) 21 Page - Microchip Technology |
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21 / 32 page  2003 Microchip Technology Inc. DS11195C-page 21 MCP41XXX/42XXX 5.5 Reset (RS) Pin Operation The Reset pin (RS) will automatically set all potentiom- eter data latches to mid-scale (Code 80h) when pulled low (provided that the pin is held low at least 150 ns and CS is high). The reset will execute regardless of the position of the SCK, SHDN and SI pins. It is possi- ble to toggle RS low and back high while SHDN is low. In this case, the potentiometer registers will reset to mid-scale, but the potentiometer will remain in shutdown mode until the SHDN pin is raised. 5.6 Shutdown (SHDN) Pin Operation When held low, the shutdown pin causes the applica- tion circuit to go into a power-saving mode by open-cir- cuiting the A terminal and shorting the B and W terminals for all potentiometers. Data register contents are not affected by entering shutdown mode (i.e., when the SHDN pin is raised, the data register contents are the same as before the shutdown mode was entered). While in shutdown mode, it is still possible to clock in new values for the data registers, as well as toggling the RS pin to cause all data registers to go to mid-scale. The new values will take affect when the SHDN pin is raised. If the device is powered-up with the SHDN pin held low, it will power-up in the shutdown mode with the data reg- isters set to mid-scale. 5.7 Power-up Considerations When the device is powered on, the data registers will be set to mid-scale (80h). A power-on reset circuit is utilized to ensure that the device powers up in this known state. Note: Bringing the RS pin low while the CS pin is low constitutes an invalid operating state and will result in indeterminate results when RS and/or CS are brought high. Note: Bringing the SHDN pin low while the CS pin is low constitutes an invalid operating state and will result in indeterminate results when SHDN and/or CS are brought high. TABLE 5-1: TRUTH TABLE FOR LOGIC INPUTS SCK CS RS SHDN Action X Ø H H Communication is initiated with device. Device comes out of standby mode. L L H H No action. Device is waiting for data to be clocked into shift register or CS to go high to execute command. ¦ L H X Shift one bit into shift register. The shift register can be loaded while the SHDN pin is low. Ø L H X Shift one bit out of shift register on the SO pin. The SO pin is active while the SHDN pin is low. X ¦ H H Based on command bits, either load data from shift register into data latches or execute shut- down command. Neither com- mand executed unless multiples of 16 clocks have been entered while CS is low. SO pin goes to a logic low. X H H H Static Operation. X H Ø H All data registers set and latched to code 80h. X H Ø L All data registers set and latched to code 80h. Device is in hardware shutdown mode and will remain in this mode. X H H Ø All potentiometers put into hardware shutdown mode; terminal A is open and W is shorted to B. X H H ¦ All potentiometers exit hard- ware shutdown mode. Potenti- ometers will also exit software shutdown mode if this rising edge occurs after a low pulse on CS. Contents of data latches are restored. |
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