 2003 Microchip Technology Inc.

DS11195C-page 13

MCP41XXX/42XXX

4.0

APPLICATIONS INFORMATION

The MCP41XXX/42XXX devices are 256 position

single and dual digital potentiometers that can be used

in place of standard mechanical pots. Resistance val-

ues of 10 k

Ω, 50 kΩ and 100 kΩ are available. As

shown in Figure 4-1, each potentiometer is made up of

a variable resistor and an 8-bit (256 position) data reg-

ister that determines the wiper position. There is a

nominal wiper resistance of 52

Ω for the 10 kΩ version,

125

Ω for the 50 kΩ and 100 kΩ versions. For the dual

devices, the channel-to-channel matching variation is

less than 1%. The resistance between the wiper and

either of the resistor endpoints varies linearly according

to the value stored in the data register. Code 00h

effectively connects the wiper to the B terminal. At

power-up, all data registers will automatically be loaded

with the mid-scale value (80h). The serial interface pro-

vides the means for loading data into the shift register,

which is then transferred to the data registers. The

serial interface also provides the means to place indi-

vidual potentiometers in the shutdown mode for maxi-

mum power savings. The SHDN pin can also be used

to put all potentiometers in shutdown mode and the RS

pin is provided to set all potentiometers to mid-scale

(80h).

FIGURE 4-1:

Block diagram showing the MCP42XXX dual digital potentiometer. Data register 0 and

data register 1 are 8-bit registers allowing 256 positions for each wiper. Standard SPI pins are used with

the addition of the Shutdown (SHDN) and Reset (RS) pins. As shown, reset affects the data register and

wipers, bringing them to mid-scale. Shutdown disconnects the A terminal and connects the wiper to B,

without changing the state of the data registers.

When laying out the circuit for your digital potentiome-

ter, bypass capacitors should be used. These capaci-

tors should be placed as close as possible to the device

pin. A bypass capacitor value of 0.1 µF is recom-

mended. Digital and analog traces should be separated

as much as possible on the board, with no traces run-

ning underneath the device or the bypass capacitor.

Extra precautions should be taken to keep traces with

high-frequency signals (such as clock lines) as far as

possible from analog traces. Use of an analog ground

plane is recommended in order to keep the ground

potential the same for all devices on the board.

RDAC1

SCK

SO

SI

Decode

Logic

16-bit Shift Register

PA0

PB0

PW0

RDAC2

Data Register 1

CS

RS

SHDN

D7

D0

Data Register 0

D7

D0

D7

D0

PA1

PB1

PW1

A

B

W

µC

To Application

Circuit

0.1 uF

0.1 uF

Data Lines