EP3SL340 datasheet(19/341 Pages) ALTERA

19 / 341 page

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

1–9

Electrical Characteristics

Altera Corporation

Stratix III Device Handbook, Volume 2

Internal Weak Pull-Up Resistor

Table 1–12 lists the weak pull-up resistor values for Stratix III devices.

I/O Standard Specifications

The following tables list input voltage sensitivities (VIH and VIL), output voltages

(VOH and VOL), and current drive characteristics (IOH and IOL) for all I/O standards

supported by Stratix III devices. VOL and VOH values are valid at the corresponding

IOL and IOH, respectively.

Table 1–13 through Table 1–18 list the Stratix III device family I/O standard

specifications. Refer to “Glossary” on page 1–326 for an explanation of terms used in

the Table 1–14 through Table 1–18.

Table 1–12. Internal Weak Pull-Up Resistor for Stratix III Devices (Note 1), (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Value of the I/O pin pull-

up resistor before and

during configuration, as

well as user mode if the

programmable pull-up

resistor option is

enabled

CCIO = 3.3 V ± 5% (2)

—25

—



CCIO = 3.0 V ± 5% (2)

—25

—



CCIO = 2.5 V ± 5% (2)

—25

—



CCIO = 1.8 V ± 5% (2)

—25

—



CCIO = 1.5 V ± 5% (2)

—25

—



CCIO = 1.2 V ± 5% (2)

—25

—



Notes to Table 1–12:

(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.

(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V

CCIO.

(3) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak

pull-down resistor is approximately 25k

.

Table 1–13. Single-Ended I/O Standards Specifications

I/O Standard

CCIO (V)

IL (V)

IH (V)

OL (V)

OH (V)

IOL

(mA)

IOH

(mA)

Min

Typ

Max

Min

Max

Min

Max

Min

3.3-V LVTTL

3.135

3.3

3.465

-0.3

0.8

1.7

3.6

0.4

2.4

-2

3.0-V LVTTL

2.85

3.15

-0.3

0.8

1.7

3.6

0.4

2.4

-2

3.3-V LVCMOS

3.135

3.3

3.465

-0.3

0.8

1.7

3.6

0.2

CCIO - 0.2

0.1

-0.1

3.0-V LVCMOS

2.85

3.15

-0.3

0.8

1.7

3.6

0.2

CCIO - 0.2

0.1

-0.1

2.5-V LVTTL/

LVCMOS

2.375

2.5

2.625

-0.3

0.7

1.7

3.6

0.2

2.1

0.1

-0.1

2.5

2.625

-0.3

0.7

1.7

3.6

0.4

-1

2.5

2.625

-0.3

0.7

1.7

3.6

0.7

1.7

-2

1.8-V LVTTL /

LVCMOS

1.71

1.8

1.89

-0.3

0.35 * V

CCIO

0.65 * V

CCIO

CCIO + 0.3

0.45

CCIO - 0.45

-2

1.5-V LVTTL/

LVCMOS

1.425

1.5

1.575

-0.3

0.35 * V

CCIO

0.65 * V

CCIO

CCIO + 0.3

0.25 * V

CCIO

0.75 * V

CCIO

2-2

1.2-V LVTTL /

LVCMOS

1.14

1.2

1.26

-0.3

0.35 * V

CCIO

0.65 * V

CCIO

CCIO + 0.3

0.25 * V

CCIO

0.75 * V

CCIO

2-2

3.0-V PCI

2.85

3.15

—

0.3 * V

CCIO

0.5 * V

CCIO

3.6

0.1 * V

CCIO

0.9 * V

CCIO

1.5

-0.5

3.0-V PCI-X

2.85

3.15

—

0.35 * V

CCIO

0.5 * V

CCIO

—0.1 * V

CCIO

0.9 * V

CCIO

1.5

-0.5

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