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EP3SL340 数据表(PDF) 27 Page - Altera Corporation |
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EP3SL340 数据表(HTML) 27 Page - Altera Corporation |
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27 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–17 Switching Characteristics © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 DSP Block Specifications Table 1–21 lists the Stratix III DSP block performance specifications. Table 1–21. DSP Block Performance Specifications for Stratix III Devices (Note 1) Mode Number of Multipliers C2 (5) C3 C4 C4L I3 I4 I4L Unit V CCL = 1.1 V V CCL = 1.1 V V CCL = 1.1 V V CCL = 1.1 V V CCL = 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V 9 9-bit multiplier (a, c, e, g) (2) 1 440 365 315 315 240 345 315 225 MHz 9 9-bit multiplier (b, d, f, h) (2) 1 500 410 375 375 270 385 375 250 MHz 12 12-bit multiplier (a, e) (3) 1 440 365 315 315 240 345 315 225 MHz 12 12-bit multiplier (b, d, f, h) (3) 1 500 410 375 375 270 385 375 250 MHz 18 18-bit multiplier 1 600 495 440 440 320 470 440 300 MHz 36 36-bit multiplier 1 440 365 315 315 220 345 315 205 MHz Double mode 1 440 365 315 315 220 345 315 205 MHz 18 18-bit multiply adder 2 490 405 345 345 250 380 345 235 MHz 18 18-bit multiply adder 4 490 405 345 345 250 380 345 235 MHz 18 18-bit multiply adder with loop back 2 490 405 345 345 250 380 345 235 MHz 18 18-bit multiply adder with loop back (4) 2 390 320 300 240 180 300 300 135 MHz 18 18-bit multiply accumulator 4 475 390 330 330 240 370 330 225 MHz 18 18-bit multiply adder with chainout 4 475 390 330 330 240 370 330 225 MHz Input Cascade Independent output of four 18 18 bit multiplier 4 550 455 415 415 270 430 415 250 MHz 36-bit shift (32 bit data) 1 475 390 330 330 250 370 330 235 MHz Notes to Table 1–21: (1) Maximum is for a fully pipelined block with Round and Saturation disabled. (2) The DSP block implements eight independent 9b 9b multiplies using a, b, c, d for the top DSP half block and e, f, g, h for the bottom DSP half block multipliers. (3) The DSP block implements six independent 12b 12b multiplies using a, b, d for the top DSP half block and e, f, h for the bottom DSP half block multipliers. (4) Maximum for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled. (5) The Fmax for the EP3SL200, EP3SE260, and EP3SL340 devices at the C2 speed grade is 7% slower than the C2 values shown in the table. |
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