ATMEGA8 datasheet(13/331 Pages) ATMEL

13 / 331 page

2486AA–AVR–02/2013

ATmega8(L)

The X-register, Y-

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect

address registers X, Y and Z are defined as described in Figure 4.

Figure 4. The X-register, Y-register and Z-Register

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the Instruction Set Reference for details).

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack

with the PUSH instruction, and it is decremented by two when the return address is pushed onto

the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by two when address is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

Instruction

Execution Timing

This section describes the general access timing concepts for instruction execution. The

Atmel

®AVR® CPU is driven by the CPU clock clk

CPU, directly generated from the selected clock

source for the chip. No internal clock division is used.

X-register

R27 (0x1B)

R26 (0x1A)

Y-register

R29 (0x1D)

R28 (0x1C)

Z-register

R31 (0x1F)

R30 (0x1E)

Bit

151413

1211

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPH

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

765

432

Read/Write

R/W

Initial Value

000

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