ATMEGA8 datasheet(49/331 Pages) ATMEL

49 / 331 page

2486AA–AVR–02/2013

ATmega8(L)

When the BOOTRST Fuse is programmed, the boot section size set to 2Kbytes, and the IVSEL

bit in the GICR Register is set before any interrupts are enabled, the most typical and general

program setup for the Reset and Interrupt Vector Addresses is:

AddressLabels

Code

Comments

;

.org $c00

$c00

rjmp

RESET

; Reset handler

$c01

rjmp

EXT_INT0

; IRQ0 Handler

$c02

rjmp

EXT_INT1

; IRQ1 Handler

...

... ;

$c12

rjmp

SPM_RDY

; Store Program Memory Ready Handler

$c13

RESET: ldi

r16,high(RAMEND); Main program start

$c14

out

SPH,r16

; Set Stack Pointer to top of RAM

$c15

ldi

r16,low(RAMEND)

$c16

out

SPL,r16

$c17

sei

; Enable interrupts

$c18

<instr>

xxx

Moving Interrupts

Between Application

and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

General Interrupt

Control Register –

GICR

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash

memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot

Loader section of the Flash. The actual address of the start of the boot Flash section is deter-

mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write

Self-Programming” on page 202 for details. To avoid unintentional changes of Interrupt Vector

tables, a special write procedure must be followed to change the IVSEL bit:

Write the Interrupt Vector Change Enable (IVCE) bit to one

Within four cycles, write the desired value to IVSEL while writing a zero to IVCE

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled

in the cycle IVCE is set, and they remain disabled until after the instruction following the write to

IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If Interrupt

Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts

are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader

Support – Read-While-Write Self-Programming” on page 202 for details on Boot Lock Bits.

Bit

654

INT1

INT0

–

IVSEL

IVCE

GICR

Read/Write

R/W

Initial Value

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