AD8033/AD8034

Rev. D | Page 19 of 24

APPLICATIONS INFORMATION

HIGH SPEED PEAK DETECTOR

The low input bias current and high bandwidth of the AD8033/

AD8034 make the parts ideal for a fast settling, low leakage peak

detector. The classic fast-low leakage topology with a diode in

the output is limited to ~1.4 V p-p maximum in the case of the

AD8033/AD8034 because of the protection diodes across the

inputs, as shown in Figure 54.

AD8033/

AD8034

~1.4V p-p MAX

Figure 54. High Speed Peak Detector with Limited Input Range

Using the AD8033/AD8034, a unity gain peak detector can

be constructed that captures a 300 ns pulse while still taking

advantage of the low input bias current and wide common-

mode input range of the AD8033/AD8034, as shown in Figure 55.

Using two amplifiers, the difference between the peak and the

current input level is forced across R2 instead of either amplifier’s

input pins. In the event of a rising pulse, the first amplifier

compensates for the drop across D2 and D3, forcing the voltage

at Node 3 equal to Node 1. D1 is off and the voltage drop across

R2 is zero. Capacitor C3 speeds up the loop by providing the

charge required by the input capacitance of the first amplifier,

helping to maintain a minimal voltage drop across R2 in the

sampling mode. A negative going edge results in D2 and D3

turning off and D1 turning on, closing the loop around the

the voltage across D2 zero, minimizing leakage current and

kickback from D3 from affecting the voltage across C2.

The rate of the incoming edge must be limited so that the output

before the output of the second amplifier can provide negative

feedback at the summing junction of the first amplifier. This

is accomplished with the combination of R1 and C1, which

The selection of C2 and R3 is made by considering droop

rate, settling time, and kickback. R3 prevents overshoot from

occurring at Node 3. The time constants of R1, C1 and R3, C2

are roughly equal to achieve the best performance. Slower time

constants can be selected by increasing C2 to minimize droop

rate and kickback at the cost of increased settling time. R1 and

C1 should also be increased to match, reducing the incoming

pulse’s effect on kickback.

AD8034

1/2

C3

10pF

R2

1kΩ

R1

1kΩ

AD8034

1/2

C1

39pF/

120pF

LS4148

R5

49.9Ω

D1

4.7pF

C4

R4

6kΩ

D3

LS4148

LS4148

R3

200Ω

C2

180pF/

560pF

D2

Figure 55. High Speed, Unity Gain Peak Detector Using AD8034