ADS1605IPAPR datasheet(8/38 Pages) TI

8 / 38 page

ADS1605

ADS1606

SBAS274H − MARCH 2003 − REVISED MAY 2007

www.ti.com

PARAMETER MEASUREMENT INFORMATION

DRDY

CLK

DOUT[15:0]

Data N + 1

Data N

Data N + 2

NOTE: CS and RD tied low.

Figure 1. Data Retrieval Timing (ADS1605, ADS1606 with FIFO Disabled)

RD, CS

DOUT[15:0]

Figure 2. DOUT Inactive/Active Timing (ADS1605, ADS1606 with FIFO Disabled)

TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

CLK period (1/fCLK)

1000

1/t1

fCLK

MHz

CLK pulse width, high or low

Rising edge of CLK to DRDY low

DRDY pulse width high or low

4 t1

Falling edge of DRDY to data invalid

Falling edge of DRDY to data valid

Rising edge of RD and/or CS inactive (high) to DOUT high impedance

Falling edge of RD and/or CS active (low) to DOUT active.

NOTE: DOUT[15:0] and DRDY load = 10pF.

ADS1605IPAPR 数据表(PDF) 8 Page - Texas Instruments

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