| 数据搜索系统,热门电子元器件搜索 |
|
ADS1605IPAPR 数据表(PDF) 25 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADS1605IPAPR 数据表(HTML) 25 Page - Texas Instruments |
|
25 / 38 page ![]() ADS1605 ADS1606 SBAS274H − MARCH 2003 − REVISED MAY 2007 www.ti.com 25 32/f CLK 128/f CLK DRDY RD Figure 24. Example of Skipping Readback when FIFO Level = 4 64/f CLK DRDY FIFO_LEV[2:0] 010 (Level = 4) Change FIFO_LEV[2:0] here 100 (Level = 8) RD 32/f CLK Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8 ANALOG POWER DISSIPATION An external resistor connected between the RBIAS pin and the analog ground sets the analog current level, as shown in Figure 26. The current is inversely proportion- al to the resistor value. Table 6 shows the recom- mended values of RBIAS for different CLK frequencies. Notice that the analog current can be reduced when us- ing a slower frequency CLK input because the modula- tor has more time to settle. Avoid adding any capaci- tance in parallel to RBIAS , since this will interfere with the internal circuitry used to set the biasing. R BIAS RBIAS AGND ADS1606 ADS1605 Figure 26. External Resistor Used to Set Analog Power Dissipation Table 6. Recommended RBIAS Resistor Values for Different CLK Frequencies fCLK DATA RATE RBIAS TYPICAL POWER DISSIPATION WITH REFEN HIGH 16MHz 2MHz 60k Ω 315mW 24MHz 3MHz 50k Ω 400mW 32MHz 4MHz 45k Ω 475mW 40MHz 5MHz 37k Ω 570mW POWER DOWN (PD) When not in use, the ADS1605/6 can be powered down by taking the PD pin low. All circuitry will be shutdown, including the voltage reference. To minimize the digital current during power down, stop the clock signal sup- plied to the CLK input. There is an internal pull-up resis- tor of 170k Ω on the PD pin, but it is recommended that this pin be connected to IOVDD if not used. If using the ADS1606 with the FIFO enabled, issue a reset after ex- iting power-down mode. Make sure to allow time for the reference to start up after exiting power-down mode. The internal reference typically requires 15ms. After the reference has stabilized, allow at least 100 DRDY cycles for the modulator and digital filter to settle before retrieving data. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |