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ADS1606IPAPR 数据表(PDF) 11 Page - Texas Instruments

部件名 ADS1606IPAPR
功能描述  16-Bit, 5MSPS Analog-to-Digital Converter
PDF  38 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

ADS1606IPAPR 数据表(HTML) 11 Page - Texas Instruments

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ADS1605
ADS1606
SBAS274H − MARCH 2003 − REVISED MAY 2007
www.ti.com
11
CLK
RESET
t
11
t
23
t
24
t
25
t
26
t
9
DRDY
RD
Figure 6. Reset Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 6
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
t9
RESET pulse width
50
ns
t11
RESET rising edge to falling edge of CLK
−5
10
ns
t23
RD pulse low after RESET goes high
8
CLK
Cycles
t24
RD pulse high before first DRDY pulse after RESET goes high
8
CLK
Cycles
t25
DRDY low after RESET goes low
8
× (FIFO level + 1)
CLK
Cycles
t26
Delay from RESET high to valid DOUT (settling to 0.001%)
See Table 4
DRDY
Cycles



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