ADS1606IPAPR datasheet(22/38 Pages) TI

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ADS1605

ADS1606

SBAS274H − MARCH 2003 − REVISED MAY 2007

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SETTLING TIME

The settling time is an important consideration when

measuring signals with large steps or when using a mul-

tiplexer in front of the analog inputs. The ADS1605/6

digital filter requires time for an instantaneous change

in signal level to propagate to the output.

Be sure to allow the filter time to settle after applying a

large step in the input signal, switching the channel on

a multiplexer placed in front of the inputs, resetting the

ADS1605/6, or exiting the power-down mode,

Figure 17 shows the settling error as a function of time

for a full-scale signal step applied at t = 0 with

2XMODE = low. This figure uses DRDY cycles (for the

ADS1605 or the ADS1606 with FIFO disabled) for the

time scale (X-axis). After 47 DRDY cycles, the settling

error drops below 0.001%. For fCLK = 40MHz, this cor-

responds to a settling time of 9.4

µs.

101

100

10−1

10−2

10−3

10−4

Settling Time (DRDY cycles)

Figure 17. Settling Time

IMPULSE RESPONSE

Figure 18 plots the normalized response for an input

applied at t = 0 with 2XMODE = low. The X-axis units of

time are DRDY cycles (for the ADS1605 or the ADS1606

with FIFO disabled)

. As shown in Figure 18, the peak of

the impulse takes 26 DRDY cycles to propagate to the

output. For fCLK = 40MHz, a DRDY cycle is 0.2µs in

duration and the propagation time (or group delay) is 26

× 0.2µs = 5.2µs.

1.0

0.8

0.6

0.4

0.2

−0.2

−0.4

Time (DRDY cycles)

Figure 18. Impulse Response

ADS1606IPAPR 数据表(PDF) 22 Page - Texas Instruments

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