Block diagram and pin connection

SPMD150STP

4/23

Doc ID 17160 Rev 1

Table 2.

Pin description

Pin N.

Name

Function

1

VSS

Logic stage supply voltage. This pin must be supplied with 3.3V or 5V source.

2REF

Voltage reference output. A voltage of 1.225V is available at this pin. It can be

used to set the output current level.

3

RESET

Reset pin. A logic level low restores the home state (State 1) on the phase

sequence generator. A 10k

Ω pull-up resistor is internally connected to VSS.

4CLOCK

Step clock. On the rising edge of this signal, the phase sequence generator

changes its state position, consequently the motor performs a step. A 10k

Ω

pull-up resistor is internally connected to VSS.

5

CW/CCW

Spin direction control input. A logic level high sets clockwise motor rotation.

A logic level Low sets counter clockwise motor rotation.Physical direction of

rotation depends on windings connection also. A 10 k

Ω pull-up resistor is

internally connected to VSS.

6VREFA

Phase A/B current setting input. Connect this pin to a properly scaled REF

(Pin2) voltage, to fix the maximum phase output current. Connecting a variable

voltage source (i.e. microcontroller DAC), it is possible to perform micro-

stepping drive.

The pin is internally connected to a 100k

Ω pull-down resistor, with a 470pF

parallel capacitor.

7

RCA

Phase A/B current controller Off-Time set pin.

Use this pin to set the desired Off-time of the switching current controller.

A 470pF capacitor and 56k

Ω resistor are internally connected between this pin

and GND1 (Pin13), giving a 16

μs -time.

8EN

Module enable input. A high logic level enables module operation.

EN (pin8) must be low, during power-up and power-down sequence, High

during normal operation. (When this input is low, the output phases are in high

impedance state, enabling the manual positioning of the motor).

A 100k

Ω pull-up resistor is internally connected to VSS.

A 100nF capacitor is internally connected to GND1

9CONTROL

Phase current decay mode selection input.

A logic level high sets the slow decay mode.

A logic level low sets the fast decay mode

A 10k

Ω pull-up resistor is internally connected to VSS.

10

HALF/FULL

Half/Full step mode selection input.

A logic level high sets the half step mode.

A logic level low sets the full step mode.

A 10k

Ω pull-up resistor is internally connected to VSS.

11

VREFB

Phase C/D current setting input.

Connect this pin to a properly scaled REF (Pin2) voltage, to fix the maximum

phase output current. Connecting a variable voltage source (i.e.

microcontroller DAC), it is possible to perform micro-stepping drive.

The pin is internally connected to a 100k

Ω pull-down resistor, with a 470pF

parallel capacitor.