AD5560JBCZ datasheet(39/68 Pages) AD

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Data Sheet

AD5560

Rev. D | Page 39 of 68

10. Calculate FZ, the ESR zero frequency, using FZ =

1/(2πRcCr).

11. If FP > Fug, the load pole is above the bandwidth of the

AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the

algorithm

12. If RC < (R0/25), then the ESR is negligible. Attempt to

cancel the load pole with RZ zero. Choose an ideal zero

frequency of 2 × FP for some safety margin and then

choose the RZ[2:0] value that gives the closest frequency on a

logarithmic scale. This ends the algorithm

13. Otherwise, this is a troublesome window in which a load

pole and a load zero can’t be ignored. Use the following

steps:

•

To cancel the load pole at FP, choose an ideal zero

frequency of 6 × FP (this is more conservative than the

2 × FP suggested earlier, but there is more that can go

wrong with miscalculation). Then choose the RZ[2:0]

value that gives the closest zero to this ideal frequency

of 6 × FP on a logarithmic scale.

•

To cancel the ESR zero at FZ, choose an ideal pole

frequency of 2 × FZ.

•

Then choose the RP[2:0] value that gives the closest pole

to this ideal frequency of 2 × FZon a logarithmic scale.

This ends the algorithm

ADJUSTING THE AUTOCOMPENSATION MODE

The autocompensation algorithm assumes that there is 1 Ω of

resistance (RC) from the AD5560 to the DUT. If a particular

application has resistance that differs greatly from this, then

it is likely that the autocompensation algorithm is nonoptimal.

If using the autocompensation algorithm as a starting point,

consider that overstating the CR capacitance and understating

the ESR RC is likely to give a faster response but could cause

oscillations. Understating CR and overstating RC is more likely

to slow things down and reduce phase margin but not create

an oscillator.

It is often advisable to err on the side of simplicity. Rather than

insert a pole and zero at similar frequencies, it may be better to

add none at all. Set RP[2:0] = RZ[2:0] = 0 to push them beyond the

AD5560 bandwidth.

DEALING WITH PARALLEL LOAD CAPACITORS

In the event that the load capacitance consists of two parallel

capacitors with different ESRs, it is highly likely that the overall

complex impedance at the unity gain bandwidth is dominated

by the larger capacitor and its ESR. Assuming that the smaller

capacitor does not exist normally is a safer simplifying assump-

tion.

A more complex alternative is to calculate the overall impedance

at the expected unity gain bandwidth and use this to calculate

an equivalent series CR and RC that have the same complex

impedance at that particular frequency.

DAC LEVELS

This device contains all the dedicated DAC levels necessary

for operation: a 16-bit DAC for the force amplifier, two 16-bit

DACs for the clamp high and low levels, two 16-bit DACs for

the comparator high and low levels, a 16-bit DAC to set a

programmable open sense voltage, and a 16-bit offset DAC

to bias or offset a number of DACs on chip (FORCE, CLL,

CLH, CPL, CPH).

FORCE AND COMPARATOR DACS

The architecture of the main force amplifier DAC consists of

a 16-bit R-2R DAC, whereas the comparator DACs are resistor-

string DACs followed by an output buffer amplifier. This

resistor-string architecture guarantees DAC monotonicity.

The 16-bit binary digital code loaded to the DAC register

determines at what node on the string the voltage is tapped

off before being fed to the output amplifier.

The comparator DAC is similarly arranged. The force and

comparator DACs have a 25.62 V span, including overrange

to enable offset and gain errors to be calibrated out.

The transfer function for these 16-bit DACs is

DUTGND

CODE

DAC

OFFSET

VREF

CODE

DAC

VREF

OUT













−













125

where DAC CODE is X2 (see the Offset and Gain Registers

section).

CLAMP DACS

The architecture of the clamp DAC consists of a 16-bit resistor-

string DAC followed by an output buffer amplifier. This resistor-

string architecture guarantees DAC monotonicity. The 16-bit

binary digital code loaded to the DAC register determines at

what node on the string the voltage is tapped off before being

fed to the output amplifier.

The clamp DACs have a 25.62 V span, including overrange, to

enable offset and gain errors to be calibrated out.

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