AD5560JBCZ datasheet(19/68 Pages) AD

19 / 68 page

Data Sheet

AD5560

Rev. D | Page 19 of 68

Pin No.

Mnemonic

Description

TMPALM

Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched

or unlatched.

CPOH/CPO

Comparator High Output (CPOH) or Window Comparator Output (CPO).

CPOL

Comparator Low Output.

EXTMEASIH2

Input High Measure Line for External High Current Range 2.

EXTMEASIH1

Input High Measure Line for External High Current Range 1.

D9,H3, J8

AVDD

Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as

measure blocks.

BUSY

Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.

SDO

Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic

purposes.

DVCC

Digital Supply Voltage.

GUARD/SYS_DUTGND

Guard Amplifier Output Pin or

System Device Under Test Ground Pin. See the DPS Register 2 in Table 19

for addressing details.

AGND

Analog Ground.

E9, G4, J4

AVSS

Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as

measure blocks.

DGND

Digital Ground Reference Point.

SCLK

Clock Input, Active Falling Edge.

SDI

Serial Data Input.

SENSE

Input Sense Line.

EXTMEASIL

Low Side Measure Current Line for External High Current Ranges.

DUTGND

Device Under Test Ground.

SYNC

Frame Sync, Active Low.

RCLK

Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied

to this input to drive the ramp circuitry. Tie RCLK low if it is unused.

RESET

Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.

CC0

Compensation Capacitor Input 0.

SYS_SENSE

External Sense Signal Output.

SYS_FORCE

External Force Signal Input.

CF2

Feedforward Capacitor 2.

CF0

Feedforward Capacitor 0.

CLEN/LOAD

Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured

as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as

LOAD input (see the system control register, Address 0x1).

VREF

Reference Input for DAC Channels, Input Range is 2 V to 5 V.

MEASOUT

Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.

CC1

Compensation Capacitor Input 1.

MASTER_OUT

Master Output When Ganging Multiple DPS Devices.

SLAVE_IN

Slave Input When Ganging Multiple DPS Devices.

CF3

Feedforward Capacitor 3.

CF1

Feedforward Capacitor 1.

HW_INH/LOAD

Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow

synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system

control register, Address 0x1).

REFGND

Accurate Ground Reference for Applied Voltage Reference.

AGND

Analog Ground.

CC3

Compensation Capacitor Input 3.

CC2

Compensation Capacitor Input 2.

FORCE

Output Force Pin for Internal Current Ranges.

CF4

Feedforward Capacitor 4.

AD5560JBCZ 数据表(PDF) 19 Page - Analog Devices

AD5560JBCZ 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载