AD8133ACP-R2 datasheet(13/16 Pages) AD

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AD8133

Rev. 0 | Page 13 of 16

CALCULATING AN APPLICATION CIRCUIT’S INPUT

IMPEDANCE

The effective input impedance of a circuit such as that in

Figure 34 at VIP and VIN depends on whether the amplifier is

being driven by a single-ended or differential signal source. For

balanced differential input signals, the differential input imped-

ance, RIN, dm, between the inputs VIP and VIN is simply

kΩ

1.5

IN,

In the case of a single-ended input signal (for example, if VIN is

grounded and the input signal is applied to VIP), the input

impedance becomes:

()

kΩ

125

⎟

⎠

⎞

⎜

⎝

⎛

−

IN,

The circuit’s input impedance is effectively higher than it would

be for a conventional op amp connected as an inverter because

a fraction of the differential output voltage appears at the inputs

as a common-mode signal, partially bootstrapping the voltage

across the input resistor RG.

INPUT COMMON-MODE VOLTAGE RANGE IN SINGLE-

SUPPLY APPLICATIONS

The inputs of the AD8133 are designed to facilitate level-

shifting of ground referenced input signals on a single power

supply. For a single-ended input, this would imply, for example,

that the voltage at VIN in Figure 34 would be 0 V when the

amplifier’s negative power supply voltage was also set to 0 V.

It is important to ensure that the common-mode voltage at the

amplifier inputs, VAP and VAN, stays within its specified range.

Since voltages VAP and VAN are driven to be essentially equal by

negative feedback, the amplifier’s input common-mode voltage

can be expressed as a single term, VACM. VACM can be calculated

as follows

2 ICM

OCM

ACM

where VICM is the common-mode voltage of the input signal, i.e.,

ICM

DRIVING A CAPACITIVE LOAD

A purely capacitive load can react with the output

impedance of the AD8133 to reduce phase margin, resulting in

high frequency ringing in the pulse response. The best way to

minimize this effect is to place a small resistor in series with

each of the amplifier’s outputs to buffer the load capacitance.

OUTPUT PULL-DOWN (OPD)

The AD8133 has an OPD pin that when pulled high signifi-

cantly reduces the power consumed while simultaneously

pulling the outputs to within less than 1 V of VS− when used

with series diodes (see the Applications section). The equivalent

schematic of the output pull-down circuit is shown in Figure 35.

(The ESD diodes shown in Figure 35 are for ESD protection and

are distinct from the series diodes used with the output pull-

down feature.) See Figure 18 and Figure 21 for the output

pull-down transient and isolation performance plots. The

threshold levels for the OPD pin are referenced to the positive

power supply voltage and are presented in the Specifications

tables. When the OPD pin is pulled high, the AD8133 enters the

output low disable state.

VOUT

ESD

DIODE

ESD

DIODE

VCC

PULLDOWN

(OUTPUT IS

PULLED DOWN

WHEN SWITCH

IS CLOSED)

VS–

VS+

Figure 35. Output Pull-Down Equivalent Circuit

OUTPUT COMMON-MODE CONTROL

The AD8133 allows the user to control each of the three

common-mode output levels independently through the three

VOCM input pins. The VOCM pins pass a signal to the common-

mode output level of each of their respective amplifiers with

330 MHz of small signal bandwidth and an internally fixed

gain of one. In this way, additional control and communication

signals can be embedded on the common-mode levels as the

user sees fit.

With no external circuitry, the level at the VOCM input of each

amplifier defaults to approximately midsupply. An internal

resistive divider with an impedance of approximately 100 kΩ

sets this level. To limit common-mode noise in dc common-

mode applications, external bypass capacitors should be

connected from each of the VOCM input pins to ground.

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