ADP2300/ADP2301

Data Sheet

Rev. C | Page 16 of 28

APPLICATIONS INFORMATION

ADIsimPower DESIGN TOOL

The ADP2300/ADP2301 are supported by the ADIsimPower

design tool set. ADIsimPower is a collection of tools that produce

complete power designs optimized for a specific design goal.

The tools enable the user to generate a full schematic and bill of

materials, and calculate performance in minutes. ADIsimPower

can optimize designs for cost, area, efficiency, and parts count

while taking into consideration the operating conditions and

limitations of the IC and all real external components. For

more information about ADIsimPower design tools, refer to

www.analog.com/ADIsimPower. The tool set is available from

this website, and users can request an unpopulated board

through the tool.

PROGRAMMING THE OUTPUT VOLTAGE

The output voltage of the ADP2300/ADP2301 is externally set by

a resistive voltage divider from the output voltage to the FB pin,

as shown in Figure 42. Suggested resistor values for the typical

output voltage setting are listed in Table 6. The equation for the

output voltage setting is













+

×

=

2

1

1

V

800

.

0

FB

FB

OUT

R

R

V

where:

ADP2300/

ADP2301

FB

Figure 42. Programming the Output Voltage Using a Resistive Voltage Divider

Table 6. Suggested Values for Resistive Voltage Divider

V

R

R

1.2

4.99

10

1.8

12.7

10.2

2.5

21.5

10.2

3.3

31.6

10.2

5.0

52.3

10

VOLTAGE CONVERSION LIMITATIONS

There are both lower and upper output voltage limitations for a

given input voltage due to the minimum on time, the minimum

off time, and the bootstrap dropout voltage.

The lower limit of the output voltage is constrained by the finite,

controllable minimum on time, which can be as high as 135 ns for

the worst case. By considering the variation of both the switching

frequency and the input voltage, the equation for the lower limit

of the output voltage is

D

D

IN

SW

ON

MIN

OUT

V

V

V

f

t

V

−

+

×

×

=

)

(

(max)

(max)

-

(min)

where:

The upper limit of the output voltage is constrained by the mini-

mum controllable off time, which can be as high as 120 ns in

the ADP2301 for the worst case. By considering the variation of

both the switching frequency and the input voltage, the equation

for the upper limit of the output voltage is

D

D

IN

SW

OFF

MIN

OUT

V

V

V

f

t

V

−

+

×

×

−

=

)

(

)

1

(

(min)

(max)

-

(max)

where:

In addition, the bootstrap circuit limits the minimum input

voltage for the desired output due to internal dropout voltage.

To attain stable operation at light loads and ensure proper startup

for the prebias condition, the ADP2300/ADP2301 require the

voltage difference between the input voltage and the regulated

output voltage (or between the input voltage and the prebias

voltage) to be greater than 2.1 V for the worst case. If the voltage

difference is smaller, the bootstrap circuit relies on some minimum

load current to charge the boost capacitor for startup. Figure 43

shows the typical required minimum input voltage vs. load current

for the 3.3 V output voltage.