AD5313 datasheet(17/24 Pages) AD

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AD5305/AD5315/AD5325

Rev. G | Page 17 of 24

Table 7. CLR and LDAC Bit Descriptions

Bit

Description

CLR

[0] All DAC registers and input registers are filled with 0s

on completion of the write sequence.

[1] Normal operation.

LDAC

[0] All four DAC registers and, therefore, all DAC outputs,

are simultaneously updated on completion of the write

sequence.

[1] Only addressed input register is updated. There is no

change in the contents of the DAC registers.

DEFAULT READBACK CONDITION

All pointer byte bits power up to 0. Therefore, if the user

initiates a readback without writing to the pointer byte first, no

single DAC channel has been specified. In this case, the default

readback bits are all 0, except for the CLR bit, which is a 1.

MULTIPLE-DAC WRITE SEQUENCE

Because there are individual bits in the pointer byte for each

DAC, it is possible to simultaneously write the same data and

control bits to 2, 3, or 4 DACs by setting the relevant bits to 1.

MULTIPLE-DAC READBACK SEQUENCE

If the user attempts to read back data from more than one DAC

at a time, the part reads back the default, power-on reset

conditions, that is, all 0s except for CLR, which is 1.

WRITE OPERATION

When writing to the AD5305/AD5315/AD5325 DACs, the user

must begin with an address byte (R/W = 0), after which the DAC

acknowledges that it is prepared to receive data by pulling SDA

low. This address byte is followed by the pointer byte, which is

also acknowledged by the DAC. Two bytes of data are then written

to the DAC, as shown in Figure 33. A stop condition follows.

READ OPERATION

When reading data back from the AD5305/AD5315/AD5325

DACs, the user begins with an address byte (R/W = 0), after

which the DAC acknowledges that it is prepared to receive data

by pulling SDA low. This address byte is usually followed by the

pointer byte, which is also acknowledged by the DAC. Following

this, there is a repeated start condition by the master and the

address is resent with R/W = 1. This is acknowledged by the

DAC indicating that it is prepared to transmit data. Two bytes

of data are then read from the DAC, as shown in Figure 34. A

stop condition follows.

However, if the master sends an ACK and continues clocking

SCL (no STOP is sent), the DAC retransmits the same two bytes

of data on SDA. This allows continuous readback of data from

the selected DAC register.

Alternatively, the user can send a start followed by the address

with R/W = 1. In this case, the previously loaded pointer settings

are used and readback of data can commence immediately.

ADDRESS BYTE

SCL

SDA

SCL

SDA

POINTER BYTE

LEAST SIGNIFICANT DATA BYTE

ACK

AD53x5

MOST SIGNIFICANT DATA BYTE

MSB

LSB

MSB

LSB

STOP

COND

MASTER

ACK

AD53x5

ACK

AD53x5

START

COND

MASTER

ACK

AD53x5

MSB

LSB

R/W

Figure 33. Write Sequence

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