AD5305/AD5315/AD5325

Rev. G | Page 21 of 24

AD5305/AD5315/AD5325 AS A DIGITALLY

PROGRAMMABLE WINDOW DETECTOR

A digitally programmable upper/lower limit detector using two

of the DACs in the AD5305/AD5315/AD5325 is shown in

Figure 39. The upper and lower limits for the test are loaded to

DAC A and DAC B, which, in turn, set the limits on the CMP04. If

an LED indicates the fail condition. Similarly, DAC C and DAC D

5V

GND

REFIN

1/6 74HC05

FAIL

PASS

1kΩ

SCL

SDA

SCL

DIN

1kΩ

0.1µF

10µF

1/2

AD5305/

AD5315/

1/2

CMP04

PASS/FAIL

Figure 39. Window Detection

COARSE AND FINE ADJUSTMENT USING THE

AD5305/AD5315/AD5325

Two of the DACs in the AD5305/AD5315/AD5325 can be paired

together to form a coarse and fine adjustment function, as shown

in Figure 40. DAC A is used to provide the coarse adjustment

while DAC B provides the fine adjustment. Varying the ratio of

R1 and R2 changes the relative effect of the coarse and fine

adjustments. With the resistor values and external reference shown

in Figure 40, the output amplifier has unity gain for the DAC A

output. As a result, the output range is 0 V to 2.5 V − 1 LSB. For

range equal to 19 mV. Similarly, DAC C and DAC D can be

paired together for coarse and fine adjustment.

The circuit is shown with a 2.5 V reference, but reference

a rail-to-rail output swing.

1µF

REFIN

GND

0.1µF

10µF

GND

5V

R3

51.2kΩ

R4

390Ω

R1

390Ω

R2

51.2kΩ

AD820/

OP295

1/2

AD5305/

AD5315/

AD780/REF192

EXT

REF

Figure 40. Coarse/Fine Adjustment

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful

consideration of the power supply and ground return layout

helps to ensure the rated performance. The printed circuit

board on which the AD5305/AD5315/AD5325 is mounted

should be designed so that the analog and digital sections are

separated and confined to certain areas of the board. If the

AD5305/AD5315/AD5325 is in a system where multiple devices

require an AGND-to-DGND connection, the connection

should be made at one point only. The star ground point should

be established as close as possible to the device. The AD5305/

AD5315/AD5325 should have ample supply bypassing of 10 μF

in parallel with 0.1 μF on the supply located as close to the

package as possible, ideally right up against the device. The

10 μF capacitors are the tantalum bead type. The 0.1 μF

capacitor should have low effective series resistance (ESR) and

effective series inductance (ESI), such as the common ceramic

types that provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

The power supply lines of the AD5305/AD5315/AD5325

should use as large a trace as possible to provide low impedance

paths and reduce the effects of glitches on the power supply

line. Fast switching signals such as clocks should be shielded

with digital ground to avoid radiating noise to other parts of the

board, and should never be run near the reference inputs. A

ground line routed between the SDA and SCL lines helps reduce

crosstalk between them (not required on a multilayer board as

there is a separate ground plane, but separating the lines does help).

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is by far the best, but is not

always possible with a double-sided board. In this technique,

the component side of the board is dedicated to ground plane

while signal traces are placed on the solder side.