LTC1293BCSW datasheet(21/28 Pages) LINER

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LTC1293/LTC1294/LTC1296

129346fs

Usually VERROR will not be significant. For a 60Hz signal

on the “–” input to generate a 0.25LSB error (300

µV) with

the converter running at CLK = 1MHz, its peak value would

have to be 66mV. Rearranging the above equation the

maximum sinusoidal signal that can be digitized to a given

accuracy is given as:

For 0.25LSB error (300

µV) the maximum input sinusoid

with a 5V peak amplitude that can be digitized is 0.8Hz.

Unused inputs should be tied to the ground plane.

Reference Input

The voltage on the reference input of the LTC1293/4/6

determines the voltage span of the A/D converter. The

reference input has transient capacitive switching cur-

rents due to the switched capacitor conversion technique

(see Figure 12). During each bit test of the conversion

(every CLK cycle) a capacitive current spike will be gener-

ated on the reference pin by the A/D. These current spikes

settle quickly and do not cause a problem. If slow settling

circuitry is used to drive the reference input, take care to

insure that transients caused by these current spikes settle

completely during each bit test of the conversion.

APPLICATI

I FOR ATIO

Figure 13 and 14 show examples of both adequate and

poor settling. Using a slower CLK will allow more time for

the reference to settle. Even at the maximum CLK rate of

1MHz most references and op amps can be made to settle

within the 1

µs bit time. For example the LT1027 will settle

adequately or with a 10

µF bypass capacitor at VREF the

LT1021 also can be used.

Figure 14. Poor Reference Settling Can Cause A/D Errors

HORIZONTAL: 1

µs/DIV

HORIZONTAL: 1

µs/DIV

Figure 13. Adequate Reference Settling (LT1027)

Figure 12. Reference Input Equivalent Circuit

RON

8pF – 40pF

LTC1293/4/6

REF+

ROUT

VREF

EVERY CLK CYCLE

REF–

LTC 1293 F12

Reduced Reference Operation

The effective resolution of the LTC1293/4/6 can be in-

creased by reducing the input span of the converter. The

LTC1293/4/6 exhibits good linearity over a range of refer-

ence voltages (see typical performance characteristics

curves of Change in Linearity vs Reference Voltage and

Change in Gain Error vs Reference Voltage). Care must be

taken when operating at low values of VREF because of the

reduced LSB step size and the resulting higher accuracy

requirement placed on the converter. Offset and Noise are

factors that must be considered when operating at low

VREF values. For the LTC1293 REF– has been tied to the

AGND pin. Any voltage drop from the AGND pin to the

ground plane will cause a gain error.

Offset with Reduced VREF

The offset of the LTC1293/4/6 has a larger effect on the

output code when the A/D is operated with a reduced

reference voltage. The offset (which is typically a fixed

voltage) becomes a larger fraction of an LSB as the size of

the LSB is reduced. The typical performance characteris-

tic curve of Unadjusted Offset Error vs Reference Voltage

shows how offset in LSB’s is related to reference voltage

for a typical value of VOS. For example a VOS of 0.1mV,

which is 0.1LSB with a 5V reference becomes 0.4LSB with

MAX

ERROR MAX

PEAK

CLK

(–)

()

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